[PATCH] D47430: TableGen: Streamline the semantics of NAME

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle added inline comments.


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Comment at: lib/Target/AArch64/AArch64InstrFormats.td:9418
 multiclass SIMDLdSt1SingleAliases<string asm> {
-  defm : SIMDLdStSingleAliases<asm, "b", "i8",  "One", 1, VectorIndexB>;
-  defm : SIMDLdStSingleAliases<asm, "h", "i16", "One", 2, VectorIndexH>;
-  defm : SIMDLdStSingleAliases<asm, "s", "i32", "One", 4, VectorIndexS>;
-  defm : SIMDLdStSingleAliases<asm, "d", "i64", "One", 8, VectorIndexD>;
+  defm "" : SIMDLdStSingleAliases<asm, "b", "i8",  "One", 1, VectorIndexB>;
+  defm "" : SIMDLdStSingleAliases<asm, "h", "i16", "One", 2, VectorIndexH>;
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tra wrote:
> `defm ""` pattern is something we should probably highlight in the docs (as examples for def/defm in a multiclass?) because it's somewhat unintuitive. We need to point that defm w/o a name will produce a unique name, while "" is effectively a synonym for NAME (IIUIC, due to rule 2).
> 
> 
I had already added a mention of this in the LangRef, but I've made it more explicit with an example.


Repository:
  rL LLVM

https://reviews.llvm.org/D47430