[PATCH] D47434: AMDGPU: Turn D16 for MIMG instructions into a regular operand

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle added a comment.

In https://reviews.llvm.org/D47434#1118807, @dp wrote:

> Regarding partial register updates: would there be any performance benefit from supporting this feature for MIMG? I.e. cannot we just ignore this feature and handle upper bits as undefined?


I believe that's effectively what we're doing today.


Repository:
  rL LLVM

https://reviews.llvm.org/D47434