[llvm] r333879 - [AArch64] Audit on rL333634 to fix FP16 Disasm BitPatterns
Luke Geeson via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 4 02:41:32 PDT 2018
Author: lukegeeson
Date: Mon Jun 4 02:41:32 2018
New Revision: 333879
URL: http://llvm.org/viewvc/llvm-project?rev=333879&view=rev
Log:
[AArch64] Audit on rL333634 to fix FP16 Disasm BitPatterns
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=333879&r1=333878&r2=333879&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Mon Jun 4 02:41:32 2018
@@ -7928,9 +7928,10 @@ multiclass SIMDFPScalarRShift<bit U, bit
let Inst{19-16} = imm{3-0};
let Inst{23-22} = 0b11;
}
- def SHr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?},
+ def SHr : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
FPR32, FPR16, vecshiftR32, asm, []> {
let Inst{19-16} = imm{3-0};
+ let Inst{22-21} = 0b01;
}
def HDr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?},
FPR16, FPR64, vecshiftR32, asm, []> {
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=333879&r1=333878&r2=333879&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Mon Jun 4 02:41:32 2018
@@ -4984,7 +4984,6 @@ def : Pat<(v1f64 (int_aarch64_neon_vcvtf
def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
(SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
-
defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
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