[PATCH] D47676: [X86][Znver1] Specify Register Files, RCU; FP scheduler capacity.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: lib/Target/X86/X86ScheduleZnver1.td:111
+// Reference: "Software Optimization Guide for AMD Family 17h Processors"
+def ZnRCU : RetireControlUnit<192, 8>;
+
----------------
GGanesh wrote:
> The retire unit is shared between integer and FP ops. In SMT mode it is 96 entry per thread. So, I think we shall consider only 96 entry as a conservative value.
Aha, i was wondering how SMT was considered here.
But then what about `MicroOpBufferSize` in `SchedMachineModel`?
Is that supposed to be keep at `192`?


================
Comment at: lib/Target/X86/X86ScheduleZnver1.td:113
+
+// FIXME: there are 72 read buffers and 44 write buffers.
+
----------------
GGanesh wrote:
> I assume these are the load/store queue entries. The FPU has
> 1. 44 entry Load Queue
> 2. 72 Out of Order Loads
> 3. 44 entry Store Queue
> So, we are concerned only about the queues, we can have only 44 marked for LD and ST.
> 
I think i would prefer to keep this just as a fixme note for now, since
while llvm-mca does have an options to specify the sizes of these queues,
it does not seem to read those from the sched model otherwise,
i guess because it can't currently be expressed here.


Repository:
  rL LLVM

https://reviews.llvm.org/D47676