[llvm] r333800 - [X86] Add isel patterns to use vexpand with zero masking when the passthru value is a zero vector.

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Fri Jun 1 15:28:29 PDT 2018


Author: ctopper
Date: Fri Jun  1 15:28:28 2018
New Revision: 333800

URL: http://llvm.org/viewvc/llvm-project?rev=333800&view=rev
Log:
[X86] Add isel patterns to use vexpand with zero masking when the passthru value is a zero vector.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrAVX512.td
    llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll
    llvm/trunk/test/CodeGen/X86/avx512vbmi2-intrinsics-fast-isel.ll
    llvm/trunk/test/CodeGen/X86/avx512vbmi2-intrinsics.ll
    llvm/trunk/test/CodeGen/X86/avx512vbmi2vl-intrinsics-fast-isel.ll
    llvm/trunk/test/CodeGen/X86/avx512vbmi2vl-intrinsics.ll
    llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll

Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=333800&r1=333799&r2=333800&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Fri Jun  1 15:28:28 2018
@@ -9409,6 +9409,10 @@ multiclass expand_by_vec_width_lowering<
             (!cast<Instruction>(NAME#_.ZSuffix##rmkz)
                                         _.KRCWM:$mask, addr:$src)>;
 
+  def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask, _.ImmAllZerosV)),
+            (!cast<Instruction>(NAME#_.ZSuffix##rmkz)
+                                        _.KRCWM:$mask, addr:$src)>;
+
   def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask,
                                                (_.VT _.RC:$src0))),
             (!cast<Instruction>(NAME#_.ZSuffix##rmk)

Modified: llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll?rev=333800&r1=333799&r2=333800&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll Fri Jun  1 15:28:28 2018
@@ -232,8 +232,7 @@ define <8 x double> @test_maskz_expand_l
 ; CHECK-LABEL: test_maskz_expand_load_pd_512:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovw %esi, %k1
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; CHECK-NEXT:    vexpandpd (%rdi), %zmm0 {%k1}
+; CHECK-NEXT:    vexpandpd (%rdi), %zmm0 {%k1} {z}
 ; CHECK-NEXT:    retq
   %res = call <8 x double> @llvm.x86.avx512.mask.expand.load.pd.512(i8* %addr, <8 x double> zeroinitializer, i8 %mask)
   ret <8 x double> %res
@@ -295,8 +294,7 @@ define <16 x float> @test_maskz_expand_l
 ; CHECK-LABEL: test_maskz_expand_load_ps_512:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovw %esi, %k1
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; CHECK-NEXT:    vexpandps (%rdi), %zmm0 {%k1}
+; CHECK-NEXT:    vexpandps (%rdi), %zmm0 {%k1} {z}
 ; CHECK-NEXT:    retq
   %res = call <16 x float> @llvm.x86.avx512.mask.expand.load.ps.512(i8* %addr, <16 x float> zeroinitializer, i16 %mask)
   ret <16 x float> %res
@@ -358,8 +356,7 @@ define <8 x i64> @test_maskz_expand_load
 ; CHECK-LABEL: test_maskz_expand_load_q_512:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovw %esi, %k1
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; CHECK-NEXT:    vpexpandq (%rdi), %zmm0 {%k1}
+; CHECK-NEXT:    vpexpandq (%rdi), %zmm0 {%k1} {z}
 ; CHECK-NEXT:    retq
   %res = call <8 x i64> @llvm.x86.avx512.mask.expand.load.q.512(i8* %addr, <8 x i64> zeroinitializer, i8 %mask)
   ret <8 x i64> %res
@@ -421,8 +418,7 @@ define <16 x i32> @test_maskz_expand_loa
 ; CHECK-LABEL: test_maskz_expand_load_d_512:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovw %esi, %k1
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; CHECK-NEXT:    vpexpandd (%rdi), %zmm0 {%k1}
+; CHECK-NEXT:    vpexpandd (%rdi), %zmm0 {%k1} {z}
 ; CHECK-NEXT:    retq
   %res = call <16 x i32> @llvm.x86.avx512.mask.expand.load.d.512(i8* %addr, <16 x i32> zeroinitializer, i16 %mask)
   ret <16 x i32> %res

Modified: llvm/trunk/test/CodeGen/X86/avx512vbmi2-intrinsics-fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vbmi2-intrinsics-fast-isel.ll?rev=333800&r1=333799&r2=333800&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vbmi2-intrinsics-fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vbmi2-intrinsics-fast-isel.ll Fri Jun  1 15:28:28 2018
@@ -237,15 +237,13 @@ define <8 x i64> @test_mm512_maskz_expan
 ; X32:       # %bb.0: # %entry
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    kmovd {{[0-9]+}}(%esp), %k1
-; X32-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; X32-NEXT:    vpexpandw (%eax), %zmm0 {%k1}
+; X32-NEXT:    vpexpandw (%eax), %zmm0 {%k1} {z}
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm512_maskz_expandloadu_epi16:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    kmovd %edi, %k1
-; X64-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; X64-NEXT:    vpexpandw (%rsi), %zmm0 {%k1}
+; X64-NEXT:    vpexpandw (%rsi), %zmm0 {%k1} {z}
 ; X64-NEXT:    retq
 entry:
   %0 = tail call <32 x i16> @llvm.x86.avx512.mask.expand.load.w.512(i8* %__P, <32 x i16> zeroinitializer, i32 %__U)
@@ -282,15 +280,13 @@ define <8 x i64> @test_mm512_maskz_expan
 ; X32-NEXT:    kmovd {{[0-9]+}}(%esp), %k1
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    kunpckdq %k1, %k0, %k1
-; X32-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; X32-NEXT:    vpexpandb (%eax), %zmm0 {%k1}
+; X32-NEXT:    vpexpandb (%eax), %zmm0 {%k1} {z}
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm512_maskz_expandloadu_epi8:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    kmovq %rdi, %k1
-; X64-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; X64-NEXT:    vpexpandb (%rsi), %zmm0 {%k1}
+; X64-NEXT:    vpexpandb (%rsi), %zmm0 {%k1} {z}
 ; X64-NEXT:    retq
 entry:
   %0 = tail call <64 x i8> @llvm.x86.avx512.mask.expand.load.b.512(i8* %__P, <64 x i8> zeroinitializer, i64 %__U)

Modified: llvm/trunk/test/CodeGen/X86/avx512vbmi2-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vbmi2-intrinsics.ll?rev=333800&r1=333799&r2=333800&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vbmi2-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vbmi2-intrinsics.ll Fri Jun  1 15:28:28 2018
@@ -15,8 +15,7 @@ define <32 x i16> @test_maskz_expand_loa
 ; CHECK-LABEL: test_maskz_expand_load_w_512:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovd %esi, %k1
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; CHECK-NEXT:    vpexpandw (%rdi), %zmm0 {%k1}
+; CHECK-NEXT:    vpexpandw (%rdi), %zmm0 {%k1} {z}
 ; CHECK-NEXT:    retq
   %res = call <32 x i16> @llvm.x86.avx512.mask.expand.load.w.512(i8* %addr, <32 x i16> zeroinitializer, i32 %mask)
   ret <32 x i16> %res
@@ -78,8 +77,7 @@ define <64 x i8> @test_maskz_expand_load
 ; CHECK-LABEL: test_maskz_expand_load_b_512:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovq %rsi, %k1
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; CHECK-NEXT:    vpexpandb (%rdi), %zmm0 {%k1}
+; CHECK-NEXT:    vpexpandb (%rdi), %zmm0 {%k1} {z}
 ; CHECK-NEXT:    retq
   %res = call <64 x i8> @llvm.x86.avx512.mask.expand.load.b.512(i8* %addr, <64 x i8> zeroinitializer, i64 %mask)
   ret <64 x i8> %res

Modified: llvm/trunk/test/CodeGen/X86/avx512vbmi2vl-intrinsics-fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vbmi2vl-intrinsics-fast-isel.ll?rev=333800&r1=333799&r2=333800&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vbmi2vl-intrinsics-fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vbmi2vl-intrinsics-fast-isel.ll Fri Jun  1 15:28:28 2018
@@ -230,15 +230,13 @@ define <2 x i64> @test_mm_maskz_expandlo
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; X32-NEXT:    kmovd %ecx, %k1
-; X32-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; X32-NEXT:    vpexpandw (%eax), %xmm0 {%k1}
+; X32-NEXT:    vpexpandw (%eax), %xmm0 {%k1} {z}
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_maskz_expandloadu_epi16:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    kmovd %edi, %k1
-; X64-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; X64-NEXT:    vpexpandw (%rsi), %xmm0 {%k1}
+; X64-NEXT:    vpexpandw (%rsi), %xmm0 {%k1} {z}
 ; X64-NEXT:    retq
 entry:
   %0 = tail call <8 x i16> @llvm.x86.avx512.mask.expand.load.w.128(i8* %__P, <8 x i16> zeroinitializer, i8 %__U)
@@ -271,15 +269,13 @@ define <2 x i64> @test_mm_maskz_expandlo
 ; X32:       # %bb.0: # %entry
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    kmovw {{[0-9]+}}(%esp), %k1
-; X32-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; X32-NEXT:    vpexpandb (%eax), %xmm0 {%k1}
+; X32-NEXT:    vpexpandb (%eax), %xmm0 {%k1} {z}
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_maskz_expandloadu_epi8:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    kmovd %edi, %k1
-; X64-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; X64-NEXT:    vpexpandb (%rsi), %xmm0 {%k1}
+; X64-NEXT:    vpexpandb (%rsi), %xmm0 {%k1} {z}
 ; X64-NEXT:    retq
 entry:
   %0 = tail call <16 x i8> @llvm.x86.avx512.mask.expand.load.b.128(i8* %__P, <16 x i8> zeroinitializer, i16 %__U)
@@ -510,15 +506,13 @@ define <4 x i64> @test_mm256_maskz_expan
 ; X32:       # %bb.0: # %entry
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    kmovw {{[0-9]+}}(%esp), %k1
-; X32-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; X32-NEXT:    vpexpandw (%eax), %ymm0 {%k1}
+; X32-NEXT:    vpexpandw (%eax), %ymm0 {%k1} {z}
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_maskz_expandloadu_epi16:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    kmovd %edi, %k1
-; X64-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; X64-NEXT:    vpexpandw (%rsi), %ymm0 {%k1}
+; X64-NEXT:    vpexpandw (%rsi), %ymm0 {%k1} {z}
 ; X64-NEXT:    retq
 entry:
   %0 = tail call <16 x i16> @llvm.x86.avx512.mask.expand.load.w.256(i8* %__P, <16 x i16> zeroinitializer, i16 %__U)
@@ -551,15 +545,13 @@ define <4 x i64> @test_mm256_maskz_expan
 ; X32:       # %bb.0: # %entry
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    kmovd {{[0-9]+}}(%esp), %k1
-; X32-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; X32-NEXT:    vpexpandb (%eax), %ymm0 {%k1}
+; X32-NEXT:    vpexpandb (%eax), %ymm0 {%k1} {z}
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_maskz_expandloadu_epi8:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    kmovd %edi, %k1
-; X64-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; X64-NEXT:    vpexpandb (%rsi), %ymm0 {%k1}
+; X64-NEXT:    vpexpandb (%rsi), %ymm0 {%k1} {z}
 ; X64-NEXT:    retq
 entry:
   %0 = tail call <32 x i8> @llvm.x86.avx512.mask.expand.load.b.256(i8* %__P, <32 x i8> zeroinitializer, i32 %__U)

Modified: llvm/trunk/test/CodeGen/X86/avx512vbmi2vl-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vbmi2vl-intrinsics.ll?rev=333800&r1=333799&r2=333800&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vbmi2vl-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vbmi2vl-intrinsics.ll Fri Jun  1 15:28:28 2018
@@ -15,8 +15,7 @@ define <8 x i16> @test_maskz_expand_load
 ; CHECK-LABEL: test_maskz_expand_load_w_128:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovd %esi, %k1
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; CHECK-NEXT:    vpexpandw (%rdi), %xmm0 {%k1}
+; CHECK-NEXT:    vpexpandw (%rdi), %xmm0 {%k1} {z}
 ; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.avx512.mask.expand.load.w.128(i8* %addr, <8 x i16> zeroinitializer, i8 %mask)
   ret <8 x i16> %res
@@ -78,8 +77,7 @@ define <16 x i8> @test_maskz_expand_load
 ; CHECK-LABEL: test_maskz_expand_load_b_128:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovd %esi, %k1
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; CHECK-NEXT:    vpexpandb (%rdi), %xmm0 {%k1}
+; CHECK-NEXT:    vpexpandb (%rdi), %xmm0 {%k1} {z}
 ; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.avx512.mask.expand.load.b.128(i8* %addr, <16 x i8> zeroinitializer, i16 %mask)
   ret <16 x i8> %res
@@ -245,8 +243,7 @@ define <16 x i16> @test_maskz_expand_loa
 ; CHECK-LABEL: test_maskz_expand_load_w_256:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovd %esi, %k1
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; CHECK-NEXT:    vpexpandw (%rdi), %ymm0 {%k1}
+; CHECK-NEXT:    vpexpandw (%rdi), %ymm0 {%k1} {z}
 ; CHECK-NEXT:    retq
   %res = call <16 x i16> @llvm.x86.avx512.mask.expand.load.w.256(i8* %addr, <16 x i16> zeroinitializer, i16 %mask)
   ret <16 x i16> %res
@@ -308,8 +305,7 @@ define <32 x i8> @test_maskz_expand_load
 ; CHECK-LABEL: test_maskz_expand_load_b_256:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovd %esi, %k1
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; CHECK-NEXT:    vpexpandb (%rdi), %ymm0 {%k1}
+; CHECK-NEXT:    vpexpandb (%rdi), %ymm0 {%k1} {z}
 ; CHECK-NEXT:    retq
   %res = call <32 x i8> @llvm.x86.avx512.mask.expand.load.b.256(i8* %addr, <32 x i8> zeroinitializer, i32 %mask)
   ret <32 x i8> %res

Modified: llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll?rev=333800&r1=333799&r2=333800&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll Fri Jun  1 15:28:28 2018
@@ -224,8 +224,7 @@ define <2 x double> @test_maskz_expand_l
 ; CHECK-LABEL: test_maskz_expand_load_pd_128:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xef,0xc0]
-; CHECK-NEXT:    vexpandpd (%rdi), %xmm0 {%k1} ## encoding: [0x62,0xf2,0xfd,0x09,0x88,0x07]
+; CHECK-NEXT:    vexpandpd (%rdi), %xmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0x89,0x88,0x07]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %res = call <2 x double> @llvm.x86.avx512.mask.expand.load.pd.128(i8* %addr, <2 x double> zeroinitializer, i8 %mask)
   ret <2 x double> %res
@@ -287,8 +286,7 @@ define <4 x float> @test_maskz_expand_lo
 ; CHECK-LABEL: test_maskz_expand_load_ps_128:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xef,0xc0]
-; CHECK-NEXT:    vexpandps (%rdi), %xmm0 {%k1} ## encoding: [0x62,0xf2,0x7d,0x09,0x88,0x07]
+; CHECK-NEXT:    vexpandps (%rdi), %xmm0 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0x89,0x88,0x07]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %res = call <4 x float> @llvm.x86.avx512.mask.expand.load.ps.128(i8* %addr, <4 x float> zeroinitializer, i8 %mask)
   ret <4 x float> %res
@@ -350,8 +348,7 @@ define <2 x i64> @test_maskz_expand_load
 ; CHECK-LABEL: test_maskz_expand_load_q_128:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xef,0xc0]
-; CHECK-NEXT:    vpexpandq (%rdi), %xmm0 {%k1} ## encoding: [0x62,0xf2,0xfd,0x09,0x89,0x07]
+; CHECK-NEXT:    vpexpandq (%rdi), %xmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0x89,0x89,0x07]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %res = call <2 x i64> @llvm.x86.avx512.mask.expand.load.q.128(i8* %addr, <2 x i64> zeroinitializer, i8 %mask)
   ret <2 x i64> %res
@@ -413,8 +410,7 @@ define <4 x i32> @test_maskz_expand_load
 ; CHECK-LABEL: test_maskz_expand_load_d_128:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xef,0xc0]
-; CHECK-NEXT:    vpexpandd (%rdi), %xmm0 {%k1} ## encoding: [0x62,0xf2,0x7d,0x09,0x89,0x07]
+; CHECK-NEXT:    vpexpandd (%rdi), %xmm0 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0x89,0x89,0x07]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %res = call <4 x i32> @llvm.x86.avx512.mask.expand.load.d.128(i8* %addr, <4 x i32> zeroinitializer, i8 %mask)
   ret <4 x i32> %res
@@ -684,8 +680,7 @@ define <4 x double> @test_maskz_expand_l
 ; CHECK-LABEL: test_maskz_expand_load_pd_256:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xef,0xc0]
-; CHECK-NEXT:    vexpandpd (%rdi), %ymm0 {%k1} ## encoding: [0x62,0xf2,0xfd,0x29,0x88,0x07]
+; CHECK-NEXT:    vexpandpd (%rdi), %ymm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xa9,0x88,0x07]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %res = call <4 x double> @llvm.x86.avx512.mask.expand.load.pd.256(i8* %addr, <4 x double> zeroinitializer, i8 %mask)
   ret <4 x double> %res
@@ -747,8 +742,7 @@ define <8 x float> @test_maskz_expand_lo
 ; CHECK-LABEL: test_maskz_expand_load_ps_256:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xef,0xc0]
-; CHECK-NEXT:    vexpandps (%rdi), %ymm0 {%k1} ## encoding: [0x62,0xf2,0x7d,0x29,0x88,0x07]
+; CHECK-NEXT:    vexpandps (%rdi), %ymm0 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0xa9,0x88,0x07]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %res = call <8 x float> @llvm.x86.avx512.mask.expand.load.ps.256(i8* %addr, <8 x float> zeroinitializer, i8 %mask)
   ret <8 x float> %res
@@ -810,8 +804,7 @@ define <4 x i64> @test_maskz_expand_load
 ; CHECK-LABEL: test_maskz_expand_load_q_256:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xef,0xc0]
-; CHECK-NEXT:    vpexpandq (%rdi), %ymm0 {%k1} ## encoding: [0x62,0xf2,0xfd,0x29,0x89,0x07]
+; CHECK-NEXT:    vpexpandq (%rdi), %ymm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xa9,0x89,0x07]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %res = call <4 x i64> @llvm.x86.avx512.mask.expand.load.q.256(i8* %addr, <4 x i64> zeroinitializer, i8 %mask)
   ret <4 x i64> %res
@@ -873,8 +866,7 @@ define <8 x i32> @test_maskz_expand_load
 ; CHECK-LABEL: test_maskz_expand_load_d_256:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xef,0xc0]
-; CHECK-NEXT:    vpexpandd (%rdi), %ymm0 {%k1} ## encoding: [0x62,0xf2,0x7d,0x29,0x89,0x07]
+; CHECK-NEXT:    vpexpandd (%rdi), %ymm0 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0xa9,0x89,0x07]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %res = call <8 x i32> @llvm.x86.avx512.mask.expand.load.d.256(i8* %addr, <8 x i32> zeroinitializer, i8 %mask)
   ret <8 x i32> %res




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