[llvm] r333764 - [DAG] Remove untriggerable check. NFCI.

[Nirav Dave via llvm-commits]

Author: niravd
Date: Fri Jun  1 08:05:05 2018
New Revision: 333764

URL: http://llvm.org/viewvc/llvm-project?rev=333764&view=rev
Log:
[DAG] Remove untriggerable check. NFCI.

Candidate check precludes this check.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=333764&r1=333763&r2=333764&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jun  1 08:05:05 2018
@@ -13647,16 +13647,6 @@ bool DAGCombiner::MergeConsecutiveStores
       unsigned FirstStoreAlign = FirstInChain->getAlignment();
       unsigned NumStoresToMerge = 1;
       for (unsigned i = 0; i < NumConsecutiveStores; ++i) {
-        StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
-        SDValue StVal = peekThroughBitcast(St->getValue());
-        // This restriction could be loosened.
-        // Bail out if any stored values are not elements extracted from a
-        // vector. It should be possible to handle mixed sources, but load
-        // sources need more careful handling (see the block of code below that
-        // handles consecutive loads).
-        if (StVal.getOpcode() != ISD::EXTRACT_VECTOR_ELT &&
-            StVal.getOpcode() != ISD::EXTRACT_SUBVECTOR)
-          return RV;
 
         // Find a legal type for the vector store.
         unsigned Elts = (i + 1) * NumMemElts;