[PATCH] D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning.

[Amara Emerson via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL333747: [AArch64][GlobalISel] Zero-extend s1 values when returning. (authored by aemerson, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D47425?vs=149282&id=149451#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D47425

Files:
  llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp
  llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll


Index: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -1859,3 +1859,14 @@
   store %agg.nested { i32 1, i32 1, %agg.inner { i16 2, i8 3, %agg.inner.inner {i64 5, i64 8} }, i32 13}, %agg.nested *%ptr
   ret void
 }
+
+define i1 @return_i1_zext() {
+; AAPCS ABI says that booleans can only be 1 or 0, so we need to zero-extend.
+; CHECK-LABEL: name: return_i1_zext
+; CHECK: [[CST:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+; CHECK: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[CST]](s1)
+; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8)
+; CHECK: $w0 = COPY [[ANYEXT]](s32)
+; CHECK: RET_ReallyLR implicit $w0
+  ret i1 true
+}
Index: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -726,17 +726,7 @@
         WideTy != LLT::scalar(8))
       return UnableToLegalize;
 
-    const auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
-    switch (TLI.getBooleanContents(false, false)) {
-    case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
-      widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_SEXT);
-      break;
-    case TargetLoweringBase::ZeroOrOneBooleanContent:
-      widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_ZEXT);
-      break;
-    default:
-      widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_ANYEXT);
-    }
+    widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_ZEXT);
     MIRBuilder.recordInsertion(&MI);
     return Legalized;
   }
Index: llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp
@@ -229,9 +229,14 @@
   assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
   bool Success = true;
   if (VReg) {
+    MachineRegisterInfo &MRI = MF.getRegInfo();
+
+    // We zero-extend i1s to i8.
+    if (MRI.getType(VReg).getSizeInBits() == 1)
+      VReg = MIRBuilder.buildZExt(LLT::scalar(8), VReg)->getOperand(0).getReg();
+
     const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
     CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
-    MachineRegisterInfo &MRI = MF.getRegInfo();
     auto &DL = F.getParent()->getDataLayout();
 
     ArgInfo OrigArg{VReg, Val->getType()};


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