[PATCH] D47434: AMDGPU: Turn D16 for MIMG instructions into a regular operand

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

dp accepted this revision.
dp added a comment.
This revision is now accepted and ready to land.

Looks good.

Regarding partial register updates: would there be any performance benefit from supporting this feature for MIMG? I.e. cannot we just ignore this feature and handle upper bits as undefined?


Repository:
  rL LLVM

https://reviews.llvm.org/D47434