[PATCH] D47589: [RISCV] Add codegen support for atomic load/stores with RV32A

[JF Bastien via Phabricator via llvm-commits]

jfb added a comment.

In https://reviews.llvm.org/D47589#1118082, @efriedma wrote:

> > Say I have two TUs which share an atomic location, but have a different idea of its alignment. They both access that location, one with libcall and one with an instruction. That's clearly broken. Can this happen?
>
> No, it's not broken (assuming the location is actually aligned at runtime). In the translation unit where the location is known aligned, it'll use the native lock-free instruction.  In the other translation unit, the libatomic call will check the alignment of the address at runtime, see it's aligned, and use a compatible lock-free implementation.


Is there a guarantee that `__atomic_*` functions start off with an alignment check, and use a compatible instruction if suitably aligned? This code <https://github.com/llvm-mirror/compiler-rt/blob/d89810afdc2862ea865f5c297ef4ea5839941d25/lib/builtins/atomic.c> doesn't seem to do so.


https://reviews.llvm.org/D47589