[llvm] r333689 - [InstCombine] narrow select to match condition operands' size
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Thu May 31 12:55:27 PDT 2018
Author: spatel
Date: Thu May 31 12:55:27 2018
New Revision: 333689
URL: http://llvm.org/viewvc/llvm-project?rev=333689&view=rev
Log:
[InstCombine] narrow select to match condition operands' size
This is the planned enhancement to D47163 / rL333611.
We want to match cmp/select sizes because that will be recognized
as min/max more easily and lead to better codegen (especially for
vector types).
As mentioned in D47163, this improves some of the tests that would
also be folded by D46380, so we may want to adjust that patch to
match the new patterns where the extend op occurs after the select.
Modified:
llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp
llvm/trunk/test/Transforms/InstCombine/minmax-fold.ll
llvm/trunk/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll
llvm/trunk/test/Transforms/InstCombine/select-obo-peo-ops.ll
Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=333689&r1=333688&r2=333689&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Thu May 31 12:55:27 2018
@@ -1164,6 +1164,11 @@ static Instruction *foldAddSubSelect(Sel
}
Instruction *InstCombiner::foldSelectExtConst(SelectInst &Sel) {
+ Constant *C;
+ if (!match(Sel.getTrueValue(), m_Constant(C)) &&
+ !match(Sel.getFalseValue(), m_Constant(C)))
+ return nullptr;
+
Instruction *ExtInst;
if (!match(Sel.getTrueValue(), m_Instruction(ExtInst)) &&
!match(Sel.getFalseValue(), m_Instruction(ExtInst)))
@@ -1173,20 +1178,18 @@ Instruction *InstCombiner::foldSelectExt
if (ExtOpcode != Instruction::ZExt && ExtOpcode != Instruction::SExt)
return nullptr;
- // TODO: Handle larger types? That requires adjusting FoldOpIntoSelect too.
+ // If we are extending from a boolean type or if we can create a select that
+ // has the same size operands as its condition, try to narrow the select.
Value *X = ExtInst->getOperand(0);
Type *SmallType = X->getType();
- if (!SmallType->isIntOrIntVectorTy(1))
- return nullptr;
-
- Constant *C;
- if (!match(Sel.getTrueValue(), m_Constant(C)) &&
- !match(Sel.getFalseValue(), m_Constant(C)))
+ Value *Cond = Sel.getCondition();
+ auto *Cmp = dyn_cast<CmpInst>(Cond);
+ if (!SmallType->isIntOrIntVectorTy(1) &&
+ (!Cmp || Cmp->getOperand(0)->getType() != SmallType))
return nullptr;
// If the constant is the same after truncation to the smaller type and
// extension to the original type, we can narrow the select.
- Value *Cond = Sel.getCondition();
Type *SelType = Sel.getType();
Constant *TruncC = ConstantExpr::getTrunc(C, SmallType);
Constant *ExtC = ConstantExpr::getCast(ExtOpcode, TruncC, SelType);
Modified: llvm/trunk/test/Transforms/InstCombine/minmax-fold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/minmax-fold.ll?rev=333689&r1=333688&r2=333689&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/minmax-fold.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/minmax-fold.ll Thu May 31 12:55:27 2018
@@ -19,9 +19,9 @@ define i64 @t1(i32 %a) {
define i64 @t2(i32 %a) {
; CHECK-LABEL: @t2(
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[A:%.*]], 5
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[A]], i32 5
-; CHECK-NEXT: [[TMP3:%.*]] = sext i32 [[TMP2]] to i64
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP1]], i32 [[A]], i32 5
+; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[NARROW]] to i64
+; CHECK-NEXT: ret i64 [[TMP2]]
;
%1 = icmp slt i32 %a, 5
%2 = sext i32 %a to i64
@@ -33,9 +33,9 @@ define i64 @t2(i32 %a) {
define i64 @t3(i32 %a) {
; CHECK-LABEL: @t3(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[A:%.*]], 5
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[A]], i32 5
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP1]], i32 [[A]], i32 5
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: ret i64 [[TMP2]]
;
%1 = icmp ult i32 %a, 5
%2 = zext i32 %a to i64
@@ -58,13 +58,12 @@ define i32 @t4(i64 %a) {
}
; Same as @t3, but with mismatched signedness between icmp and zext.
-; InstCombine should leave this alone.
define i64 @t5(i32 %a) {
; CHECK-LABEL: @t5(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[A:%.*]], 5
-; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[A]] to i64
-; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP1]], i64 5, i64 [[TMP2]]
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[A:%.*]], 5
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP1]], i32 [[A]], i32 5
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: ret i64 [[TMP2]]
;
%1 = icmp slt i32 %a, 5
%2 = zext i32 %a to i64
Modified: llvm/trunk/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll?rev=333689&r1=333688&r2=333689&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll Thu May 31 12:55:27 2018
@@ -5,11 +5,11 @@ define i64 @sel_false_val_is_a_masked_sh
; CHECK-LABEL: @sel_false_val_is_a_masked_shl_of_true_val1(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, 15
%2 = shl nuw nsw i32 %1, 2
@@ -41,11 +41,11 @@ define i64 @sel_false_val_is_a_masked_ls
; CHECK-LABEL: @sel_false_val_is_a_masked_lshr_of_true_val1(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 60
; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, 60
%2 = lshr i32 %1, 2
@@ -77,11 +77,11 @@ define i64 @sel_false_val_is_a_masked_as
; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val1(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483588
; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, -2147483588
%2 = ashr i32 %1, 2
Modified: llvm/trunk/test/Transforms/InstCombine/select-obo-peo-ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-obo-peo-ops.ll?rev=333689&r1=333688&r2=333689&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-obo-peo-ops.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/select-obo-peo-ops.ll Thu May 31 12:55:27 2018
@@ -5,11 +5,11 @@ define i64 @test_shl_nuw_nsw__all_are_sa
; CHECK-LABEL: @test_shl_nuw_nsw__all_are_safe(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, 15
%2 = shl nuw nsw i32 %1, 2
@@ -24,11 +24,11 @@ define i64 @test_shl_nuw__all_are_safe(i
; CHECK-LABEL: @test_shl_nuw__all_are_safe(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, 15
%2 = shl nuw i32 %1, 2
@@ -43,11 +43,11 @@ define i64 @test_shl_nsw__all_are_safe(i
; CHECK-LABEL: @test_shl_nsw__all_are_safe(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, 15
%2 = shl nsw i32 %1, 2
@@ -62,11 +62,11 @@ define i64 @test_shl__all_are_safe(i32 %
; CHECK-LABEL: @test_shl__all_are_safe(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, 15
%2 = shl i32 %1, 2
@@ -81,11 +81,11 @@ define i64 @test_shl_nuw_nsw__nuw_is_saf
; CHECK-LABEL: @test_shl_nuw_nsw__nuw_is_safe(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, 1073741822
%2 = shl nuw nsw i32 %1, 2
@@ -100,11 +100,11 @@ define i64 @test_shl_nuw__nuw_is_safe(i3
; CHECK-LABEL: @test_shl_nuw__nuw_is_safe(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, 1073741822
%2 = shl nuw i32 %1, 2
@@ -119,11 +119,11 @@ define i64 @test_shl_nsw__nuw_is_safe(i3
; CHECK-LABEL: @test_shl_nsw__nuw_is_safe(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, 1073741822
%2 = shl nsw i32 %1, 2
@@ -138,11 +138,11 @@ define i64 @test_shl__nuw_is_safe(i32 %x
; CHECK-LABEL: @test_shl__nuw_is_safe(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, 1073741822
%2 = shl i32 %1, 2
@@ -234,11 +234,11 @@ define i64 @test_shl_nuw_nsw__none_are_s
; CHECK-LABEL: @test_shl_nuw_nsw__none_are_safe(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, 4294967294
%2 = shl nuw nsw i32 %1, 2
@@ -253,11 +253,11 @@ define i64 @test_shl_nuw__none_are_safe(
; CHECK-LABEL: @test_shl_nuw__none_are_safe(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, 4294967294
%2 = shl nuw i32 %1, 2
@@ -272,11 +272,11 @@ define i64 @test_shl_nsw__none_are_safe(
; CHECK-LABEL: @test_shl_nsw__none_are_safe(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2
; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, 4294967294
%2 = shl nsw i32 %1, 2
@@ -289,13 +289,11 @@ define i64 @test_shl_nsw__none_are_safe(
define i64 @test_shl__none_are_safe(i32 %x, i64 %y) {
; CHECK-LABEL: @test_shl__none_are_safe(
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2
-; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT: ret i64 [[TMP4]]
;
%1 = and i32 %x, 4294967294
%2 = shl i32 %1, 2
@@ -310,11 +308,11 @@ define i64 @test_lshr_exact__exact_is_sa
; CHECK-LABEL: @test_lshr_exact__exact_is_safe(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 60
; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, 60
%2 = lshr exact i32 %1, 2
@@ -329,11 +327,11 @@ define i64 @test_lshr__exact_is_safe(i32
; CHECK-LABEL: @test_lshr__exact_is_safe(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 60
; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, 60
%2 = lshr i32 %1, 2
@@ -348,11 +346,11 @@ define i64 @test_lshr_exact__exact_is_un
; CHECK-LABEL: @test_lshr_exact__exact_is_unsafe(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 63
; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, 63
%2 = lshr exact i32 %1, 2
@@ -365,13 +363,11 @@ define i64 @test_lshr_exact__exact_is_un
define i64 @test_lshr__exact_is_unsafe(i32 %x, i64 %y) {
; CHECK-LABEL: @test_lshr__exact_is_unsafe(
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 63
-; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT: ret i64 [[TMP4]]
;
%1 = and i32 %x, 63
%2 = lshr i32 %1, 2
@@ -386,11 +382,11 @@ define i64 @test_ashr_exact__exact_is_sa
; CHECK-LABEL: @test_ashr_exact__exact_is_safe(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483588
; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, -2147483588
%2 = ashr exact i32 %1, 2
@@ -405,11 +401,11 @@ define i64 @test_ashr__exact_is_safe(i32
; CHECK-LABEL: @test_ashr__exact_is_safe(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483588
; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, -2147483588
%2 = ashr i32 %1, 2
@@ -424,11 +420,11 @@ define i64 @test_ashr_exact__exact_is_un
; CHECK-LABEL: @test_ashr_exact__exact_is_unsafe(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483585
; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
;
%1 = and i32 %x, -2147483585
%2 = ashr exact i32 %1, 2
@@ -441,13 +437,11 @@ define i64 @test_ashr_exact__exact_is_un
define i64 @test_ashr__exact_is_unsafe(i32 %x, i64 %y) {
; CHECK-LABEL: @test_ashr__exact_is_unsafe(
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483585
-; CHECK-NEXT: [[TMP2:%.*]] = ashr i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
-; CHECK-NEXT: ret i64 [[TMP6]]
+; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT: ret i64 [[TMP4]]
;
%1 = and i32 %x, -2147483585
%2 = ashr i32 %1, 2
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