[PATCH] D47589: [RISCV] Add codegen support for atomic load/stores with RV32A

[Alex Bradbury via Phabricator via llvm-commits]

asb created this revision.
asb added reviewers: jyknight, theraven, jfb, eli.friedman.
Herald added subscribers: mgrang, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar.

Fences are inserted according to table A.6 in the current draft <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20180531-40cf935/riscv-spec.pdf> of version 2.3 of the RISC-V Instruction Set Manual, which incorporates the memory model changes and definitions contributed by the RISC-V Memory Consistency Model
task group.

When the A extension is supported, __atomic libcalls will be generated for any atomic that isn't the native word size or has less than natural alignment. This relies on the hook added in https://reviews.llvm.org/D47553. Instruction selection failures will now occur for 32-bit atomicrmw and cmpxchg operations when targeting RV32IA until lowering for these operations is added in a follow-on patch.


https://reviews.llvm.org/D47589

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  lib/Target/RISCV/RISCVInstrInfo.td
  lib/Target/RISCV/RISCVInstrInfoA.td
  test/CodeGen/RISCV/atomic-fence.ll
  test/CodeGen/RISCV/atomic-load-store.ll

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