[PATCH] D47120: [NEON] Support VLD1xN intrinsics in AArch32 mode (LLVM part)

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer accepted this revision.
SjoerdMeijer added a comment.
This revision is now accepted and ready to land.

Like I said in https://reviews.llvm.org/D47121, I agree that these intrinsics are available in v7/A32/A64.
This change looks reasonable to me.



================
Comment at: lib/Target/ARM/ARMExpandPseudoInsts.cpp:468
+    // case, fixed forms do not take any offset nodes, so here we skip them for
+    // such intructions. Once all real and pseudo writing-back instructions are
+    // rewritten without use of am6offset nodes, this code will go away.
----------------
typo: intructions


https://reviews.llvm.org/D47120