[PATCH] D47582: [mips] Select the correct instruction for computing frameindexes

[Simon Dardis via Phabricator via llvm-commits]

sdardis created this revision.
sdardis added reviewers: smaksimovic, atanasyan, abeserminji.
Herald added a subscriber: arichardson.

Repository:
  rL LLVM

https://reviews.llvm.org/D47582

Files:
  lib/Target/Mips/MicroMipsInstrInfo.td
  lib/Target/Mips/MicroMipsSizeReduction.cpp
  lib/Target/Mips/Mips64InstrInfo.td
  lib/Target/Mips/MipsInstrInfo.td
  test/CodeGen/Mips/frameindex.ll


Index: test/CodeGen/Mips/frameindex.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Mips/frameindex.ll
@@ -0,0 +1,20 @@
+; RUN: llc -mtriple=mips-mti-linux-gnu < %s -debug 2>&1 | FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips-mti-linux-gnu -mattr=+micromips < %s -debug 2>&1 | FileCheck %s --check-prefix=MM
+; RUN: llc -mtriple=mips64-mti-linux-gnu < %s -debug 2>&1 | FileCheck %s --check-prefix=MIPS64
+
+; REQUIRES: asserts
+
+; CHECK-LABEL: Instruction selection ends:
+
+; MIPS32: t{{[0-9]+}}: i{{[0-9]+}} = LEA_ADDiu TargetFrameIndex:i32<0>, TargetConstant:i32<0>
+; MM: t{{[0-9]+}}: i{{[0-9]+}} = LEA_ADDiu_MM TargetFrameIndex:i32<0>, TargetConstant:i32<0>
+; MIPS64: t{{[0-9]+}}: i{{[0-9]+}} = LEA_ADDiu64 TargetFrameIndex:i64<0>, TargetConstant:i64<0>
+
+define i32 @k() {
+entry:
+  %h = alloca i32, align 4
+  %call = call i32 @g(i32* %h)
+  ret i32 %call
+}
+
+declare i32 @g(i32*)
Index: lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsInstrInfo.td
+++ lib/Target/Mips/MipsInstrInfo.td
@@ -2309,7 +2309,8 @@
 // instructions. The same not happens for stack address copies, so an
 // add op with mem ComplexPattern is used and the stack address copy
 // can be matched. It's similar to Sparc LEA_ADDRi
-def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
+let AdditionalPredicates = [NotInMicroMips] in
+  def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>, ISA_MIPS1;
 
 // MADD*/MSUB*
 def MADD  : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
Index: lib/Target/Mips/Mips64InstrInfo.td
===================================================================
--- lib/Target/Mips/Mips64InstrInfo.td
+++ lib/Target/Mips/Mips64InstrInfo.td
@@ -323,9 +323,10 @@
              ISA_MIPS64R2;
   def DSHD : SubwordSwap<"dshd", GPR64Opnd, II_DSHD>, SEB_FM<5, 0x24>,
              ISA_MIPS64R2;
+
+  def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
 }
 
-def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
 
 let isCodeGenOnly = 1 in
 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
Index: lib/Target/Mips/MicroMipsSizeReduction.cpp
===================================================================
--- lib/Target/Mips/MicroMipsSizeReduction.cpp
+++ lib/Target/Mips/MicroMipsSizeReduction.cpp
@@ -200,6 +200,8 @@
      OpInfo(OT_OperandsAll), ImmField(0, -1, 15, 2)},
     {RT_OneInstr, OpCodes(Mips::LEA_ADDiu, Mips::ADDIUR1SP_MM),
      ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
+    {RT_OneInstr, OpCodes(Mips::LEA_ADDiu_MM, Mips::ADDIUR1SP_MM),
+     ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
     {RT_OneInstr, OpCodes(Mips::LHu, Mips::LHU16_MM), ReduceLXUtoLXU16,
      OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
     {RT_OneInstr, OpCodes(Mips::LHu_MM, Mips::LHU16_MM), ReduceLXUtoLXU16,
Index: lib/Target/Mips/MicroMipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMipsInstrInfo.td
+++ lib/Target/Mips/MicroMipsInstrInfo.td
@@ -749,7 +749,7 @@
                  ISA_MICROMIPS32_NOT_MIPS32R6;
 
   def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
-                     LW_FM_MM<0xc>;
+                     LW_FM_MM<0xc>, ISA_MICROMIPS;
 
   /// Arithmetic Instructions (3-Operand, R-Type)
   def ADDu_MM  : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,


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