[llvm] r333622 - AMDGPU/R600: Make sure functions are cacheline aligned
Jan Vesely via llvm-commits
llvm-commits at lists.llvm.org
Wed May 30 21:08:08 PDT 2018
Author: jvesely
Date: Wed May 30 21:08:08 2018
New Revision: 333622
URL: http://llvm.org/viewvc/llvm-project?rev=333622&view=rev
Log:
AMDGPU/R600: Make sure functions are cacheline aligned
v2: use "ensureAlignment"
make functions cache line aligned
Fixes GPU hangs since r333219:
"AMDGPU: Split R600 AsmPrinter code into its own class"
Differential Revision: https://reviews.llvm.org/D47516
Added:
llvm/trunk/test/CodeGen/AMDGPU/r600.func-alignment.ll
Modified:
llvm/trunk/lib/Target/AMDGPU/R600AsmPrinter.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/R600AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/R600AsmPrinter.cpp?rev=333622&r1=333621&r2=333622&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/R600AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/R600AsmPrinter.cpp Wed May 30 21:08:08 2018
@@ -103,6 +103,10 @@ void R600AsmPrinter::EmitProgramInfoR600
bool R600AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
+
+ // Functions needs to be cacheline (256B) aligned.
+ MF.ensureAlignment(8);
+
SetupMachineFunction(MF);
MCContext &Context = getObjFileLowering().getContext();
Added: llvm/trunk/test/CodeGen/AMDGPU/r600.func-alignment.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/r600.func-alignment.ll?rev=333622&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/r600.func-alignment.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/r600.func-alignment.ll Wed May 30 21:08:08 2018
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=rs880 | FileCheck %s
+
+; CHECK: .globl test
+; Functions need to be cacheline (256B) aligned to prevent GPU hangs
+; CHECK: .p2align 8
+; CHECK: {{^}}test:
+; CHECK: CF_END
+
+define amdgpu_ps void @test(<4 x float> inreg %reg0) {
+entry:
+ ret void
+}
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