[PATCH] D47523: [X86] Extract latency of fldz/fld1 in separate classes.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: lib/Target/X86/X86InstrFPStack.td:658
 def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", []>;
 def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>;
 def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>;
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Please pull these 5 FLD* entries out and classify as WriteFLDC (see X86Schedule.td)


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Comment at: lib/Target/X86/X86Schedule.td:146
+def  WriteF80Constant0  : SchedWrite;
+def  WriteF80Constant1  : SchedWrite;
 def  WriteFLoadX        : SchedWrite;
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Shorten the names to WriteFLD0, WriteFLD1, - allows you to remove all the indentation changes.

Please add WriteFLDC for the other math constants (FLDPI etc.)


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Comment at: lib/Target/X86/X86ScheduleBtVer2.td:275
+defm : X86WriteRes<WriteF80Constant0,  [JFPU1], 1, [1], 1>;
+defm : X86WriteRes<WriteF80Constant1,  [JFPU1], 1, [1], 1>;
 defm : X86WriteRes<WriteFLoad,         [JLAGU, JFPU01, JFPX], 5, [1, 1, 1], 1>;
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Checked with the AMD16h SOG - these should be [JFPU1, JSTC], 3, [1,1,], 1


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Comment at: lib/Target/X86/X86ScheduleZnver1.td:818
-// FLDZ.
-def : InstRW<[ZnWriteFPU13], (instregex "LD_F0")>;
-
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Just replace these with SchedAlias instead of entries above - that's what is mainly used in znver1


Repository:
  rL LLVM

https://reviews.llvm.org/D47523