[PATCH] D47377: [X86][Sched] Fix WriteZero sched class for all CPUs.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: lib/Target/X86/X86SchedBroadwell.td:159
 // These can often bypass execution ports completely.
-def : WriteRes<WriteZero,  []>;
+def : WriteRes<WriteZero,    []> {
+  let Latency = 0;
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You can make all of these tidier by using the X86WriteRes multiclass:
```
defm : X86WriteRes<WriteZero, [], 0, [], 0>;
```


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Comment at: test/CodeGen/X86/avx512-intrinsics-upgrade.ll:2
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
 
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General intrinsics/combines tests shouldn't typically be dependent on a specific cpu model - it causes superfluous changes like these - I'll fix the tests shortly.


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Comment at: utils/TableGen/GlobalISelEmitter.cpp:1987
-  return {};
-}
-
----------------
Should this be here?


Repository:
  rL LLVM

https://reviews.llvm.org/D47377