[PATCH] D46837: [MachineScheduler] Skip an implicit def of a super-reg added by regalloc in findDefIdx.

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa added a comment.

It seems that the reason this problem occurs for me, is that the target is lazily just calling setDesc() on an instruction to change the opcode, and then adds one extra register. For example, a load may become load-and-test, which just means that the opcode changes and the CC register is defined also.

An alternative way of handling this in MachineInstr::addOperand() is now at: https://reviews.llvm.org/D47524.

It seems to me that we could either:

1. Fix findDefIdx per this patch. The mapping of SchedWrite order to operand order is already in need of a separate lookup, so this might not be so bad.
2. Fix addOperand() per https://reviews.llvm.org/D47524, so that target is free to think about MCInstrDesc and InstrRW for the instruction without interference from super-reg implicit defs etc.
3. Demand of target that it has to build the instruction with the right operand order. This is a bit of extra work for the target: it has to rebuild from scratch and also transfer any non-MCInstrDesc operands to the new instruction.


https://reviews.llvm.org/D46837