[llvm] r333405 - [mips] Correct the predicates for a number of instructions.
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Tue May 29 02:56:19 PDT 2018
Author: sdardis
Date: Tue May 29 02:56:19 2018
New Revision: 333405
URL: http://llvm.org/viewvc/llvm-project?rev=333405&view=rev
Log:
[mips] Correct the predicates for a number of instructions.
Previously, their listed predicates were overridden at the scope level.
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D46947
Modified:
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
llvm/trunk/test/MC/Mips/micromips-16-bit-instructions.s
llvm/trunk/test/MC/Mips/micromips/valid.s
llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s
llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=333405&r1=333404&r2=333405&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Tue May 29 02:56:19 2018
@@ -652,8 +652,10 @@ def ADDIUR1SP_MM : AddImmUR1SP<"addiur1s
def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
-def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
-def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
+def MFHI16_MM : MoveFromHILOMM<"mfhi16", GPR32Opnd, AC0>,
+ MFHILO_FM_MM16<0x10>;
+def MFLO16_MM : MoveFromHILOMM<"mflo16", GPR32Opnd, AC0>,
+ MFHILO_FM_MM16<0x12>;
def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16,
ISA_MICROMIPS_NOT_32R6;
@@ -860,7 +862,7 @@ let DecoderNamespace = "MicroMips" in {
II_SWR>, LWL_FM_MM<0x9>,
ISA_MICROMIPS32_NOT_MIPS32R6;
}
-let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
+let DecoderNamespace = "MicroMips" in {
/// Load and Store Instructions - multiple
def SWM32_MM : StoreMultMM<"swm32", II_SWM>, LWM_FM_MM<0xd>, ISA_MICROMIPS;
def LWM32_MM : LoadMultMM<"lwm32", II_LWM>, LWM_FM_MM<0x5>, ISA_MICROMIPS;
@@ -893,22 +895,25 @@ let DecoderNamespace = "MicroMips", Pred
CMov_F_I_FM_MM<0x25>, ISA_MICROMIPS32_NOT_MIPS32R6;
def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
CMov_F_I_FM_MM<0x5>, ISA_MICROMIPS32_NOT_MIPS32R6;
-
/// Move to/from HI/LO
def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
- MTLO_FM_MM<0x0b5>;
+ MTLO_FM_MM<0x0b5>, ISA_MICROMIPS32_NOT_MIPS32R6;
def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
- MTLO_FM_MM<0x0f5>;
+ MTLO_FM_MM<0x0f5>, ISA_MICROMIPS32_NOT_MIPS32R6;
def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
- MFLO_FM_MM<0x035>;
+ MFLO_FM_MM<0x035>, ISA_MICROMIPS32_NOT_MIPS32R6;
def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
- MFLO_FM_MM<0x075>;
+ MFLO_FM_MM<0x075>, ISA_MICROMIPS32_NOT_MIPS32R6;
/// Multiply Add/Sub Instructions
- def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
- def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
- def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
- def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
+ def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>,
+ ISA_MICROMIPS32_NOT_MIPS32R6;
+ def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>,
+ ISA_MICROMIPS32_NOT_MIPS32R6;
+ def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>,
+ ISA_MICROMIPS32_NOT_MIPS32R6;
+ def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>,
+ ISA_MICROMIPS32_NOT_MIPS32R6;
/// Count Leading
def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM_MM<0x16c>,
@@ -924,22 +929,21 @@ let DecoderNamespace = "MicroMips", Pred
/// Word Swap Bytes Within Halfwords
def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>,
- SEB_FM_MM<0x1ec>, ISA_MIPS32R2;
+ SEB_FM_MM<0x1ec>, ISA_MICROMIPS;
// TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5,
- immZExt5Plus1, MipsExt>, EXT_FM_MM<0x2c>;
+ immZExt5Plus1, MipsExt>, EXT_FM_MM<0x2c>,
+ ISA_MICROMIPS32_NOT_MIPS32R6;
def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1,
immZExt5, immZExt5Plus1>,
- EXT_FM_MM<0x0c>;
+ EXT_FM_MM<0x0c>, ISA_MICROMIPS32_NOT_MIPS32R6;
/// Jump Instructions
-}
-let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeJumpTargetMM" in
- def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
- J_FM_MM<0x35>, AdditionalRequires<[RelocNotPIC]>,
- IsBranch, ISA_MICROMIPS32_NOT_MIPS32R6;
+ let DecoderMethod = "DecodeJumpTargetMM" in
+ def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
+ J_FM_MM<0x35>, AdditionalRequires<[RelocNotPIC]>,
+ IsBranch, ISA_MICROMIPS32_NOT_MIPS32R6;
-let DecoderNamespace = "MicroMips" in {
let DecoderMethod = "DecodeJumpTargetMM" in {
def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>,
ISA_MICROMIPS32_NOT_MIPS32R6;
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll?rev=333405&r1=333404&r2=333405&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll Tue May 29 02:56:19 2018
@@ -205,8 +205,8 @@ entry:
; 64R6: dmul $2, $4, $5
; MM32R3: multu $[[T0:[0-9]+]], $7
- ; MM32R3: mflo $[[T1:[0-9]+]]
- ; MM32R3: mfhi $[[T2:[0-9]+]]
+ ; MM32R3: mflo16 $[[T1:[0-9]+]]
+ ; MM32R3: mfhi16 $[[T2:[0-9]+]]
; MM32R3: mul $[[T0]], $[[T0]], $6
; MM32R3: addu16 $2, $[[T2]], $[[T0]]
; MM32R3: mul $[[T3:[0-9]+]], $4, $7
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll?rev=333405&r1=333404&r2=333405&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll Tue May 29 02:56:19 2018
@@ -50,7 +50,7 @@ entry:
; MMR3: div $zero, $4, $5
; MMR3: teq $5, $zero, 7
- ; MMR3: mflo $[[T0:[0-9]+]]
+ ; MMR3: mflo16 $[[T0:[0-9]+]]
; MMR3: andi16 $[[T0]], $[[T0]], 1
; MMR3: li16 $[[T1:[0-9]+]], 0
; MMR3: subu16 $2, $[[T1]], $[[T0]]
@@ -89,7 +89,7 @@ entry:
; MMR3: div $zero, $4, $5
; MMR3: teq $5, $zero, 7
- ; MMR3: mflo $[[T0:[0-9]+]]
+ ; MMR3: mflo16 $[[T0:[0-9]+]]
; MMR3: seb $2, $[[T0]]
; MMR6: div $[[T0:[0-9]+]], $4, $5
@@ -124,7 +124,7 @@ entry:
; MMR3: div $zero, $4, $5
; MMR3: teq $5, $zero, 7
- ; MMR3: mflo $[[T0:[0-9]+]]
+ ; MMR3: mflo16 $[[T0:[0-9]+]]
; MMR3: seh $2, $[[T0]]
; MMR6: div $[[T0:[0-9]+]], $4, $5
@@ -148,7 +148,7 @@ entry:
; MMR3: div $zero, $4, $5
; MMR3: teq $5, $zero, 7
- ; MMR3: mflo $2
+ ; MMR3: mflo16 $2
; MMR6: div $2, $4, $5
; MMR6: teq $5, $zero, 7
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll?rev=333405&r1=333404&r2=333405&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll Tue May 29 02:56:19 2018
@@ -48,7 +48,7 @@ entry:
; MMR3: div $zero, $4, $5
; MMR3: teq $5, $zero, 7
- ; MMR3: mfhi $[[T0:[0-9]+]]
+ ; MMR3: mfhi16 $[[T0:[0-9]+]]
; MMR3: andi16 $[[T0]], $[[T0]], 1
; MMR3: li16 $[[T1:[0-9]+]], 0
; MMR3: subu16 $2, $[[T1]], $[[T0]]
@@ -84,7 +84,7 @@ entry:
; MMR3: div $zero, $4, $5
; MMR3: teq $5, $zero, 7
- ; MMR3: mfhi $[[T0:[0-9]+]]
+ ; MMR3: mfhi16 $[[T0:[0-9]+]]
; MMR3: seb $2, $[[T0]]
; MMR6: mod $[[T0:[0-9]+]], $4, $5
@@ -116,7 +116,7 @@ entry:
; MMR3: div $zero, $4, $5
; MMR3: teq $5, $zero, 7
- ; MMR3: mfhi $[[T0:[0-9]+]]
+ ; MMR3: mfhi16 $[[T0:[0-9]+]]
; MMR3: seh $2, $[[T0]]
; MMR6: mod $[[T0:[0-9]+]], $4, $5
@@ -140,7 +140,7 @@ entry:
; MMR3: div $zero, $4, $5
; MMR3: teq $5, $zero, 7
- ; MMR3: mfhi $2
+ ; MMR3: mfhi16 $2
; MMR6: mod $2, $4, $5
; MMR6: teq $5, $zero, 7
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll?rev=333405&r1=333404&r2=333405&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll Tue May 29 02:56:19 2018
@@ -44,7 +44,7 @@ entry:
; MMR3: divu $zero, $4, $5
; MMR3: teq $5, $zero, 7
- ; MMR3: mflo $2
+ ; MMR3: mflo16 $2
; MMR6: divu $2, $4, $5
; MMR6: teq $5, $zero, 7
@@ -66,7 +66,7 @@ entry:
; MMR3: divu $zero, $4, $5
; MMR3: teq $5, $zero, 7
- ; MMR3: mflo $2
+ ; MMR3: mflo16 $2
; MMR6: divu $2, $4, $5
; MMR6: teq $5, $zero, 7
@@ -88,7 +88,7 @@ entry:
; MMR3: divu $zero, $4, $5
; MMR3: teq $5, $zero, 7
- ; MMR3: mflo $2
+ ; MMR3: mflo16 $2
; MMR6: divu $2, $4, $5
; MMR6: teq $5, $zero, 7
@@ -110,7 +110,7 @@ entry:
; MMR3: divu $zero, $4, $5
; MMR3: teq $5, $zero, 7
- ; MMR3: mflo $2
+ ; MMR3: mflo16 $2
; MMR6: divu $2, $4, $5
; MMR6: teq $5, $zero, 7
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll?rev=333405&r1=333404&r2=333405&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll Tue May 29 02:56:19 2018
@@ -53,7 +53,7 @@ entry:
; MMR3: andi16 $[[T1:[0-9]+]], $4, 1
; MMR3: divu $zero, $[[T1]], $[[T0]]
; MMR3: teq $[[T0]], $zero, 7
- ; MMR3: mfhi $[[T2:[0-9]+]]
+ ; MMR3: mfhi16 $[[T2:[0-9]+]]
; MMR3: andi16 $[[T0]], $[[T0]], 1
; MMR3: li16 $[[T1:[0-9]+]], 0
; MMR3: subu16 $2, $[[T1]], $[[T0]]
@@ -98,7 +98,7 @@ entry:
; MMR3: andi16 $[[T1:[0-9]+]], $4, 255
; MMR3: divu $zero, $[[T1]], $[[T0]]
; MMR3: teq $[[T0]], $zero, 7
- ; MMR3: mfhi $[[T2:[0-9]+]]
+ ; MMR3: mfhi16 $[[T2:[0-9]+]]
; MMR3: seb $2, $[[T2]]
; MMR6: andi16 $[[T0:[0-9]+]], $5, 255
@@ -140,7 +140,7 @@ entry:
; MMR3: andi16 $[[T1:[0-9]+]], $4, 65535
; MMR3: divu $zero, $[[T1]], $[[T0]]
; MMR3: teq $[[T0]], $zero, 7
- ; MMR3: mfhi $[[T2:[0-9]+]]
+ ; MMR3: mfhi16 $[[T2:[0-9]+]]
; MMR3: seh $2, $[[T2]]
; MMR6: andi16 $[[T0:[0-9]+]], $5, 65535
@@ -166,7 +166,7 @@ entry:
; MMR3: divu $zero, $4, $5
; MMR3: teq $5, $zero, 7
- ; MMR3: mfhi $2
+ ; MMR3: mfhi16 $2
; MMR6: modu $2, $4, $5
; MMR6: teq $5, $zero, 7
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt?rev=333405&r1=333404&r2=333405&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt Tue May 29 02:56:19 2018
@@ -24,8 +24,8 @@
0x14 0xaa # CHECK: sh16 $4, 8($17)
0x11 0xea # CHECK: sw16 $4, 4($17)
0x11 0xe8 # CHECK: sw16 $zero, 4($17)
-0x09 0x46 # CHECK: mfhi $9
-0x49 0x46 # CHECK: mflo $9
+0x09 0x46 # CHECK: mfhi16 $9
+0x49 0x46 # CHECK: mflo16 $9
0x21 0x0f # CHECK: move $25, $1
0x9a 0x85 # CHECK: movep $4, $21, $18, $17
0xa9 0x45 # CHECK: jrc $9
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt?rev=333405&r1=333404&r2=333405&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt Tue May 29 02:56:19 2018
@@ -24,8 +24,8 @@
0xaa 0x14 # CHECK: sh16 $4, 8($17)
0xea 0x11 # CHECK: sw16 $4, 4($17)
0xe8 0x11 # CHECK: sw16 $zero, 4($17)
-0x46 0x09 # CHECK: mfhi $9
-0x46 0x49 # CHECK: mflo $9
+0x46 0x09 # CHECK: mfhi16 $9
+0x46 0x49 # CHECK: mflo16 $9
0x0f 0x21 # CHECK: move $25, $1
0x85 0x9a # CHECK: movep $4, $21, $18, $17
0x45 0xa9 # CHECK: jrc $9
Modified: llvm/trunk/test/MC/Mips/micromips-16-bit-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-16-bit-instructions.s?rev=333405&r1=333404&r2=333405&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-16-bit-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-16-bit-instructions.s Tue May 29 02:56:19 2018
@@ -40,8 +40,8 @@
# CHECK-EL: addiusp 1024 # encoding: [0x01,0x4c]
# CHECK-EL: addiusp 1028 # encoding: [0x03,0x4c]
# CHECK-EL: addiusp -16 # encoding: [0xf9,0x4f]
-# CHECK-EL: mfhi $9 # encoding: [0x09,0x46]
-# CHECK-EL: mflo $9 # encoding: [0x49,0x46]
+# CHECK-EL: mfhi16 $9 # encoding: [0x09,0x46]
+# CHECK-EL: mflo16 $9 # encoding: [0x49,0x46]
# CHECK-EL: move $25, $1 # encoding: [0x21,0x0f]
# CHECK-EL: movep $5, $6, $2, $3 # encoding: [0x34,0x84]
# CHECK-EL: jrc $9 # encoding: [0xa9,0x45]
@@ -95,8 +95,8 @@
# CHECK-EB: addiusp 1024 # encoding: [0x4c,0x01]
# CHECK-EB: addiusp 1028 # encoding: [0x4c,0x03]
# CHECK-EB: addiusp -16 # encoding: [0x4f,0xf9]
-# CHECK-EB: mfhi $9 # encoding: [0x46,0x09]
-# CHECK-EB: mflo $9 # encoding: [0x46,0x49]
+# CHECK-EB: mfhi16 $9 # encoding: [0x46,0x09]
+# CHECK-EB: mflo16 $9 # encoding: [0x46,0x49]
# CHECK-EB: move $25, $1 # encoding: [0x0f,0x21]
# CHECK-EB: movep $5, $6, $2, $3 # encoding: [0x84,0x34]
# CHECK-EB: jrc $9 # encoding: [0x45,0xa9]
@@ -148,8 +148,8 @@
addiusp 1024
addiusp 1028
addiusp -16
- mfhi $9
- mflo $9
+ mfhi16 $9
+ mflo16 $9
move $25, $1
movep $5, $6, $2, $3
jrc $9
Modified: llvm/trunk/test/MC/Mips/micromips/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips/valid.s?rev=333405&r1=333404&r2=333405&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips/valid.s Tue May 29 02:56:19 2018
@@ -24,8 +24,8 @@ sb16 $3, 4($16) # CHECK: sb1
sh16 $4, 8($17) # CHECK: sh16 $4, 8($17) # encoding: [0xaa,0x14]
sw16 $4, 4($17) # CHECK: sw16 $4, 4($17) # encoding: [0xea,0x11]
sw16 $zero, 4($17) # CHECK: sw16 $zero, 4($17) # encoding: [0xe8,0x11]
-mfhi $9 # CHECK: mfhi $9 # encoding: [0x46,0x09]
-mflo $9 # CHECK: mflo $9 # encoding: [0x46,0x49]
+mfhi16 $9 # CHECK: mfhi16 $9 # encoding: [0x46,0x09]
+mflo16 $9 # CHECK: mflo16 $9 # encoding: [0x46,0x49]
move $25, $1 # CHECK: move $25, $1 # encoding: [0x0f,0x21]
jrc $9 # CHECK: jrc $9 # encoding: [0x45,0xa9]
jalr $9 # CHECK: jalr $9 # encoding: [0x45,0xc9]
@@ -133,10 +133,10 @@ movt $9, $6, $fcc0 # CHECK: mov
movf $9, $6, $fcc0 # CHECK: movf $9, $6, $fcc0 # encoding: [0x55,0x26,0x01,0x7b]
# FIXME: MTHI should also have its 16 bit implementation selected in micromips
mthi $6 # CHECK: mthi $6 # encoding: [0x00,0x06,0x2d,0x7c]
-mfhi $6 # CHECK: mfhi $6 # encoding: [0x46,0x06]
+mfhi $6 # CHECK: mfhi $6 # encoding: [0x00,0x06,0x0d,0x7c]
# FIXME: MTLO should also have its 16 bit implementation selected in micromips
mtlo $6 # CHECK: mtlo $6 # encoding: [0x00,0x06,0x3d,0x7c]
-mflo $6 # CHECK: mflo $6 # encoding: [0x46,0x46]
+mflo $6 # CHECK: mflo $6 # encoding: [0x00,0x06,0x1d,0x7c]
mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x54,0x80,0x30,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D32_MM
mthc1 $4, $f0 # CHECK: mthc1 $4, $f0 # encoding: [0x54,0x80,0x38,0x3b]
Modified: llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s?rev=333405&r1=333404&r2=333405&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s Tue May 29 02:56:19 2018
@@ -28,3 +28,7 @@
sc $4, -513($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
ll $4, 512($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
ll $4, -513($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ lwr $4, 1($5) # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+ lwl $4, 1($5) # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+ swr $4, 1($5) # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+ swl $4, 1($5) # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/invalid.s?rev=333405&r1=333404&r2=333405&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s Tue May 29 02:56:19 2018
@@ -382,3 +382,11 @@
lwc2 $1, 16($32) # CHECK: :[[@LINE]]:15: error: invalid register number
sdc2 $1, 8($32) # CHECK: :[[@LINE]]:14: error: invalid register number
swc2 $1, 777($32) # CHECK: :[[@LINE]]:16: error: invalid register number
+ movn $3, $3, $4 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ movz $3, $3, $4 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ movt $4, $5, $fcc0 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ movf $4, $5, $fcc0 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ madd $4, $5 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ maddu $4, $5 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ msub $4, $5 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ msubu $4, $5 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=333405&r1=333404&r2=333405&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Tue May 29 02:56:19 2018
@@ -117,8 +117,10 @@
# CHECK-NEXT: # <MCInst #{{.*}} PREF_MMR6
sb16 $3, 4($16) # CHECK: sb16 $3, 4($16) # encoding: [0x89,0x84]
seb $3, $4 # CHECK: seb $3, $4 # encoding: [0x00,0x64,0x2b,0x3c]
+ # CHECK-NEXT: # <MCInst #{{.*}} SEB_MM
seb $3 # CHECK: seb $3, $3 # encoding: [0x00,0x63,0x2b,0x3c]
seh $3, $4 # CHECK: seh $3, $4 # encoding: [0x00,0x64,0x3b,0x3c]
+ # CHECK-NEXT: # <MCInst #{{.*}} SEH_MM
seh $3 # CHECK: seh $3, $3 # encoding: [0x00,0x63,0x3b,0x3c]
seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x83,0x11,0x40]
selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x83,0x11,0x80]
@@ -363,9 +365,11 @@
bc2eqzc $31, 8 # CHECK: bc2eqzc $31, 8 # encoding: [0x41,0x5f,0x00,0x04]
bc2nezc $31, 8 # CHECK: bc2nezc $31, 8 # encoding: [0x41,0x7f,0x00,0x04]
ins $9, $6, 3, 7 # CHECK: ins $9, $6, 3, 7 # encoding: [0x01,0x26,0x48,0xcc]
+ # CHECK-NEXT: # <MCInst #{{.*}} INS_MMR6
jalrc $4, $5 # CHECK: jalrc $4, $5 # encoding: [0x00,0x85,0x0f,0x3c]
jalrc $5 # CHECK: jalrc $5 # encoding: [0x03,0xe5,0x0f,0x3c]
ext $9, $6, 3, 7 # CHECK: ext $9, $6, 3, 7 # encoding: [0x01,0x26,0x30,0xec]
+ # CHECK-NEXT: # <MCInst #{{.*}} EXT_MMR6
bovc $2, $4, 24 # CHECK: bovc $2, $4, 24 # encoding: [0x74,0x44,0x00,0x0c]
bovc $4, $2, 24 # CHECK: bovc $4, $2, 24 # encoding: [0x74,0x44,0x00,0x0c]
bnvc $2, $4, 24 # CHECK: bnvc $2, $4, 24 # encoding: [0x7c,0x44,0x00,0x0c]
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