[PATCH] D47434: AMDGPU: Turn D16 for MIMG instructions into a regular operand

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

I was thinking of actually moving the opposite direction for these. For modeling partial register updates, I think having operands for all of these is unmanageable.  The problem is worse for ALU instructions with the zero high bit control bit. I think the same issues apply here. What is the behavior for the high bits if only 1 or 3 components are enabled?


Repository:
  rL LLVM

https://reviews.llvm.org/D47434