[llvm] r333374 - [PowerPC] Set isAsmParserOnly=1 for X-form TLS loads/stores
Zaara Syeda via llvm-commits
llvm-commits at lists.llvm.org
Mon May 28 08:27:59 PDT 2018
Author: syzaara
Date: Mon May 28 08:27:58 2018
New Revision: 333374
URL: http://llvm.org/viewvc/llvm-project?rev=333374&view=rev
Log:
[PowerPC] Set isAsmParserOnly=1 for X-form TLS loads/stores
The X-form TLS load/store instructions added for optimizing the initial-exec
sequence in https://reviews.llvm.org/rL327635 fail to assemble. llvm-mc fails
with the error: invalid operand for instruction. This patch adds these
instructions into a block with isAsmParserOnly, similar to how ADD8TLS_ is
currently handled.
Differential Revision: https://reviews.llvm.org/D47382
Modified:
llvm/trunk/lib/Target/PowerPC/P9InstrResources.td
llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/trunk/test/MC/PowerPC/ppc64-tls-relocs-01.s
Modified: llvm/trunk/lib/Target/PowerPC/P9InstrResources.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/P9InstrResources.td?rev=333374&r1=333373&r2=333374&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/P9InstrResources.td (original)
+++ llvm/trunk/lib/Target/PowerPC/P9InstrResources.td Mon May 28 08:27:58 2018
@@ -736,13 +736,13 @@ def : InstRW<[P9_LS_4C, IP_AGEN_1C, DISP
(instregex "ICBI(EP)?$"),
(instregex "ICBT(LS)?$"),
(instregex "LBARX(L)?$"),
- (instregex "LBZ(CIX|8|X|X8|XTLS|XTLS_32)?$"),
- (instregex "LD(ARX|ARXL|BRX|CIX|X|XTLS)?$"),
+ (instregex "LBZ(CIX|8|X|X8|XTLS|XTLS_32)?(_)?$"),
+ (instregex "LD(ARX|ARXL|BRX|CIX|X|XTLS)?(_)?$"),
(instregex "LH(A|B)RX(L)?(8)?$"),
- (instregex "LHZ(8|CIX|X|X8|XTLS|XTLS_32)?$"),
+ (instregex "LHZ(8|CIX|X|X8|XTLS|XTLS_32)?(_)?$"),
(instregex "LWARX(L)?$"),
(instregex "LWBRX(8)?$"),
- (instregex "LWZ(8|CIX|X|X8|XTLS|XTLS_32)?$"),
+ (instregex "LWZ(8|CIX|X|X8|XTLS|XTLS_32)?(_)?$"),
CP_ABORT,
DARN,
EnforceIEIO,
@@ -894,7 +894,7 @@ def : InstRW<[P9_LS_1C, IP_EXEC_1C, IP_A
(instregex "(D|X)FSTORE(f32|f64)$"),
(instregex "ST(W|H|D)BRX$"),
(instregex "ST(B|H|D)(8)?$"),
- (instregex "ST(B|W|H|D)(CI)?X(TLS|TLS_32)?(8)?$"),
+ (instregex "ST(B|W|H|D)(CI)?X(TLS|TLS_32)?(8)?(_)?$"),
STIWX,
SLBIEG,
STMW,
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=333374&r1=333373&r2=333374&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Mon May 28 08:27:58 2018
@@ -600,10 +600,37 @@ defm SUBFZE8 : XOForm_3rc<31, 200, 0, (o
// FIXME: Duplicating this for the asm parser should be unnecessary, but the
// previous definition must be marked as CodeGen only to prevent decoding
// conflicts.
-let isAsmParserOnly = 1 in
+let isAsmParserOnly = 1 in {
def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
"add $rT, $rA, $rB", IIC_IntSimple, []>;
+let mayLoad = 1 in {
+def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
+ "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>;
+def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
+ "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>;
+def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
+ "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>;
+def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
+ "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64;
+}
+
+let mayStore = 1 in {
+def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
+ "stbx $rS, $rA, $rB", IIC_LdStStore, []>,
+ PPC970_DGroup_Cracked;
+def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
+ "sthx $rS, $rA, $rB", IIC_LdStStore, []>,
+ PPC970_DGroup_Cracked;
+def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
+ "stwx $rS, $rA, $rB", IIC_LdStStore, []>,
+ PPC970_DGroup_Cracked;
+def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
+ "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64,
+ PPC970_DGroup_Cracked;
+}
+}
+
let isCommutable = 1 in {
defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"mulhd", "$rT, $rA, $rB", IIC_IntMulHW,
Modified: llvm/trunk/test/MC/PowerPC/ppc64-tls-relocs-01.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-tls-relocs-01.s?rev=333374&r1=333373&r2=333374&view=diff
==============================================================================
--- llvm/trunk/test/MC/PowerPC/ppc64-tls-relocs-01.s (original)
+++ llvm/trunk/test/MC/PowerPC/ppc64-tls-relocs-01.s Mon May 28 08:27:58 2018
@@ -4,7 +4,16 @@
.text
addis 3, 13, t at tprel@ha
addi 3, 3, t at tprel@l
-
+ addis 3, 2, t at got@tprel at ha
+ ld 3, t at got@tprel at l(3)
+ lwzx 4, 3, t at tls
+ lhzx 4, 3, t at tls
+ lbzx 4, 3, t at tls
+ ldx 4, 3, t at tls
+ stbx 4, 3, t at tls
+ sthx 4, 3, t at tls
+ stwx 4, 3, t at tls
+ stdx 4, 3, t at tls
.type t, at object
.section .tbss,"awT", at nobits
.globl t
@@ -19,4 +28,14 @@ t:
# CHECK: Section ({{[0-9]+}}) .rela.text {
# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TPREL16_HA t
# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TPREL16_LO t
+# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_HA t 0x0
+# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_LO_DS t 0x0
+# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
+# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
+# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
+# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
+# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
+# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
+# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
+# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
# CHECK-NEXT: }
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