[PATCH] D47425: [GlobalISel][Legalizer] Fix i1s being sign extended instead of zero-extended
Amara Emerson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun May 27 09:14:39 PDT 2018
aemerson created this revision.
aemerson added reviewers: dsanders, rtereshin.
Herald added subscribers: kristof.beyls, rovka.
Herald added a reviewer: javed.absar.
We need to ask the targets how they want bools represented bitwise, to know which kind of extension we do when we legalize i1s to a wider type.
Fixes PR36719
Repository:
rL LLVM
https://reviews.llvm.org/D47425
Files:
lib/CodeGen/GlobalISel/LegalizerHelper.cpp
test/CodeGen/AArch64/GlobalISel/legalize-bool.mir
Index: test/CodeGen/AArch64/GlobalISel/legalize-bool.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AArch64/GlobalISel/legalize-bool.mir
@@ -0,0 +1,33 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=aarch64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+ target triple = "aarch64-linux-gnu"
+
+ define i1 @test() {
+ entry:
+ ret i1 true
+ }
+
+
+...
+---
+name: test
+alignment: 2
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.1.entry:
+ ; CHECK-LABEL: name: test
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK: $w0 = COPY [[COPY]](s32)
+ ; CHECK: RET_ReallyLR implicit $w0
+ %0:_(s1) = G_CONSTANT i1 true
+ %1:_(s32) = G_ANYEXT %0(s1)
+ $w0 = COPY %1(s32)
+ RET_ReallyLR implicit $w0
+
+...
Index: lib/CodeGen/GlobalISel/LegalizerHelper.cpp
===================================================================
--- lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -743,8 +743,17 @@
case TargetOpcode::G_CONSTANT: {
MachineOperand &SrcMO = MI.getOperand(1);
LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
- const APInt &Val = SrcMO.getCImm()->getValue().sext(WideTy.getSizeInBits());
- SrcMO.setCImm(ConstantInt::get(Ctx, Val));
+ APInt Val = SrcMO.getCImm()->getValue();
+ APInt WideVal;
+ const auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
+ if (Val.getBitWidth() == 1 &&
+ (TLI.getBooleanContents(false, false) ==
+ TargetLoweringBase::ZeroOrOneBooleanContent)) {
+ WideVal = Val.zext(WideTy.getSizeInBits());
+ } else {
+ WideVal = Val.sext(WideTy.getSizeInBits());
+ }
+ SrcMO.setCImm(ConstantInt::get(Ctx, WideVal));
widenScalarDst(MI, WideTy);
MIRBuilder.recordInsertion(&MI);
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