[llvm] r333296 - [llvm-mca] Update DispatchStage header comment. NFC.

[Matt Davis via llvm-commits]

Author: mattd
Date: Fri May 25 11:31:28 2018
New Revision: 333296

URL: http://llvm.org/viewvc/llvm-project?rev=333296&view=rev
Log:
[llvm-mca] Update DispatchStage header comment. NFC.

Updated the comment to be a wee bit more descriptive.

Modified:
    llvm/trunk/tools/llvm-mca/DispatchStage.cpp
    llvm/trunk/tools/llvm-mca/DispatchStage.h

Modified: llvm/trunk/tools/llvm-mca/DispatchStage.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/DispatchStage.cpp?rev=333296&r1=333295&r2=333296&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/DispatchStage.cpp (original)
+++ llvm/trunk/tools/llvm-mca/DispatchStage.cpp Fri May 25 11:31:28 2018
@@ -8,7 +8,11 @@
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// This file implements methods declared by the DispatchStage class.
+/// This file models the dispatch component of an instruction pipeline.
+///
+/// The DispatchStage is responsible for updating instruction dependencies
+/// and communicating to the simulated instruction scheduler that an instruction
+/// is ready to be scheduled for execution.
 ///
 //===----------------------------------------------------------------------===//
 

Modified: llvm/trunk/tools/llvm-mca/DispatchStage.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/DispatchStage.h?rev=333296&r1=333295&r2=333296&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/DispatchStage.h (original)
+++ llvm/trunk/tools/llvm-mca/DispatchStage.h Fri May 25 11:31:28 2018
@@ -8,8 +8,11 @@
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// This file implements classes that are used to model reorder buffers and
-/// the hardware dispatch logic.
+/// This file models the dispatch component of an instruction pipeline.
+///
+/// The DispatchStage is responsible for updating instruction dependencies
+/// and communicating to the simulated instruction scheduler that an instruction
+/// is ready to be scheduled for execution.
 ///
 //===----------------------------------------------------------------------===//