[PATCH] D47362: [X86][Sched] Add InstRW for CLC on Intel after SNB.

[Clement Courbet via Phabricator via llvm-commits]

courbet added a comment.

Thanks. Now I'll guess I'll go fix the WriteZero definition, that has one uop and latency 1 because that's the default :(


Repository:
  rL LLVM

https://reviews.llvm.org/D47362