[PATCH] D47362: [X86][Sched] Add InstRW for CLC on Intel after SNB.

[Clement Courbet via Phabricator via llvm-commits]

courbet created this revision.
courbet added reviewers: craig.topper, RKSimon.

After SNB, Intel CPUs can rename CF independently of other EFLAGS,
so the renamer can zero it for free. Note that STC still consumes resources.

To reproduce: `$ llvm-exegesis -mode=uops -opcode-name=CLC`

On SNB:

  ---
  key:
    opcode_name:     CLC
    mode:            uops
    config:          ''
  cpu_name:        sandybridge
  llvm_triple:     x86_64-unknown-linux-gnu
  num_repetitions: 10000
  measurements:
    - { key: '3', value: 0.0014, debug_string: SBPort0 }
    - { key: '4', value: 0.0013, debug_string: SBPort1 }
    - { key: '5', value: 0.0003, debug_string: SBPort4 }
    - { key: '6', value: 0.0029, debug_string: SBPort5 }
    - { key: '10', value: 0.0003, debug_string: SBPort23 }
  error:           ''
  info:            'instruction is serial, repeating a random one.
  Snippet:
  CLC
  '
  ...

On HSW:

  ---
  key:
    opcode_name:     CLC
    mode:            uops
    config:          ''
  cpu_name:        haswell
  llvm_triple:     x86_64-unknown-linux-gnu
  num_repetitions: 10000
  measurements:
    - { key: '3', value: 0.001, debug_string: HWPort0 }
    - { key: '4', value: 0.0009, debug_string: HWPort1 }
    - { key: '5', value: 0.0004, debug_string: HWPort2 }
    - { key: '6', value: 0.0006, debug_string: HWPort3 }
    - { key: '7', value: 0.0002, debug_string: HWPort4 }
    - { key: '8', value: 0.0012, debug_string: HWPort5 }
    - { key: '9', value: 0.0022, debug_string: HWPort6 }
    - { key: '10', value: 0.0001, debug_string: HWPort7 }
  error:           ''
  info:            'instruction is serial, repeating a random one.
  Snippet:
  CLC
  '
  ...


Repository:
  rL LLVM

https://reviews.llvm.org/D47362

Files:
  lib/Target/X86/X86SchedBroadwell.td
  lib/Target/X86/X86SchedHaswell.td
  lib/Target/X86/X86SchedSandyBridge.td
  lib/Target/X86/X86SchedSkylakeClient.td
  lib/Target/X86/X86SchedSkylakeServer.td


Index: lib/Target/X86/X86SchedSkylakeServer.td
===================================================================
--- lib/Target/X86/X86SchedSkylakeServer.td
+++ lib/Target/X86/X86SchedSkylakeServer.td
@@ -606,7 +606,7 @@
   let ResourceCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE,
-                                          CLC, CMC, STC)>;
+                                          CMC, STC)>;
 def: InstRW<[SKXWriteResGroup10], (instrs LAHF, SAHF)>; // TODO: This doesn't match Agner's data
 def: InstRW<[SKXWriteResGroup10], (instregex "NOOP",
                                              "SGDT64m",
@@ -2550,4 +2550,7 @@
   let ResourceCycles = [1,3];
 }
 def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>;
+
+def: InstRW<[WriteZero], (instrs CLC)>;
+
 } // SchedModel
Index: lib/Target/X86/X86SchedSkylakeClient.td
===================================================================
--- lib/Target/X86/X86SchedSkylakeClient.td
+++ lib/Target/X86/X86SchedSkylakeClient.td
@@ -584,7 +584,7 @@
   let ResourceCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE,
-                                          CLC, CMC, STC)>;
+                                          CMC, STC)>;
 def: InstRW<[SKLWriteResGroup10], (instrs LAHF, SAHF)>; // TODO: This doesn't match Agner's data
 def: InstRW<[SKLWriteResGroup10], (instregex "NOOP",
                                              "SGDT64m",
@@ -1839,4 +1839,6 @@
 }
 def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>;
 
+def: InstRW<[WriteZero], (instrs CLC)>;
+
 } // SchedModel
Index: lib/Target/X86/X86SchedSandyBridge.td
===================================================================
--- lib/Target/X86/X86SchedSandyBridge.td
+++ lib/Target/X86/X86SchedSandyBridge.td
@@ -1152,4 +1152,6 @@
 }
 def: InstRW<[SBWriteResGroup131], (instregex "DIV(R?)_FI(16|32)m")>;
 
+def: InstRW<[WriteZero], (instrs CLC)>;
+
 } // SchedModel
Index: lib/Target/X86/X86SchedHaswell.td
===================================================================
--- lib/Target/X86/X86SchedHaswell.td
+++ lib/Target/X86/X86SchedHaswell.td
@@ -866,7 +866,7 @@
   let ResourceCycles = [1];
 }
 def: InstRW<[HWWriteResGroup10], (instrs CBW, CWDE, CDQE,
-                                         CLC, CMC, STC)>;
+                                         CMC, STC)>;
 def: InstRW<[HWWriteResGroup10], (instrs LAHF, SAHF)>; // TODO: This doesn't match Agner's data
 def: InstRW<[HWWriteResGroup10], (instregex "NOOP",
                                             "SGDT64m",
@@ -1958,4 +1958,6 @@
 def: InstRW<[HWWriteResGroup192], (instrs VGATHERQPSrm,
                                           VGATHERDPSrm)>;
 
+def: InstRW<[WriteZero], (instrs CLC)>;
+
 } // SchedModel
Index: lib/Target/X86/X86SchedBroadwell.td
===================================================================
--- lib/Target/X86/X86SchedBroadwell.td
+++ lib/Target/X86/X86SchedBroadwell.td
@@ -1682,5 +1682,7 @@
 }
 def: InstRW<[BWWriteResGroup202], (instrs FSTENVm)>;
 
+def: InstRW<[WriteZero], (instrs CLC)>;
+
 } // SchedModel
 


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