[PATCH] D47330: [DAGCombiner] match vector compare and select sizes with extload operand (PR37427)

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: craig.topper, RKSimon, efriedma.
Herald added a subscriber: mcrosier.

This patch started off much more general and ambitious, but it's been a nightmare seeing all the ways x86 vector codegen can go wrong.

So the code is still structured to allow extending easily, but it's currently limited in several ways:

1. Only handle cases with an extending load.
2. Only handle cases with a zero constant compare.
3. Ignore setcc with vector bitmask (SetCCWidth != 1) - so AVX512 should be unaffected.

The motivating case from PR37427:
https://bugs.llvm.org/show_bug.cgi?id=37427
...is the 1st test, and that shows the expected win - we eliminated the unnecessary intermediate cast.

There's a clear regression in the last test (sgt_zero_fp_select) because we longer recognize a 'SHRUNKBLEND' opportunity. I think that general problem is also present in sgt_zero, so I'm hoping we can fix that more generally in a follow-up. We need to match a sign-bit setcc from a sign-extended operand and remove it.


https://reviews.llvm.org/D47330

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/X86/vsel-cmp-load.ll

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