[PATCH] D46118: [RISCV] AsmParser support for the li pseudo instruction

[Mario Werner via Phabricator via llvm-commits]

niosHD added a comment.

In case it helps, my reasoning is as follows. There are basically two situations which can occur:

1. ADDI(W) is the first instruction of the expanded li and the source register is x0.  The ADDIW instruction, as used before, would calculate the result as `SignExtend64<32>(x0 + SignExtend64<12>(imm))`. Considering that x0 is always 0, the result is therefore simply ``SignExtend64<32>(SignExtend64<12>(imm)) = SignExtend64<12>(imm)` which is also what the ADDI instruction gives us. (i.e., `x0+SignExtend64<12>(imm) = SignExtend64<12>(imm) `)
2. The ADDI(W) instruction follows a LUI instruction. The LUI instruction itself already performs sign extension to 64-bit meaning that the input register to the ADDI(W) instruction is a proper 64-bit signed value where the upper 32 bits are a copy of bit 31 (the MSB of the LUI immediate). Using LUI+ADDIW therefore calculates  `SignExtend64<32>(SignExtend64<32>(lui_imm << 12) + SignExtend64<12>(addi_imm)))`. Using LUI+ADDI gets us `SignExtend64<32>(lui_imm << 12) + SignExtend64<12>(addi_imm))` which should be the same result in the end.

HTH,
Mario


https://reviews.llvm.org/D46118