[PATCH] D47012: [X86] Scalar mask and scalar move optimizations

[Tomasz Krupa via Phabricator via llvm-commits]

tkrupa added inline comments.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:32216
+        Mask = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, Mask);
+      return DAG.getNode(ISD::SELECT, DL, VT, Mask, RHS, LHS);
+    }
----------------
craig.topper wrote:
> I don't know if you can use ISD::SELECT here if you don't have the ANDing with 1. ISD::SELECT definition is that the condition value is either 0 or 1 regardless of how many bits it is. If you pass in the raw X you violate this rule.
I think I can - X86TargetLowering::LowerSELECT takes care of that when operands are scalar and subtarget has AVX512 which is always the case here. I'm talking about this code:

  // AVX512 fallback is to lower selects of scalar floats to masked moves.
  if ((VT == MVT::f64 || VT == MVT::f32) && Subtarget.hasAVX512()) {
    SDValue Cmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v1i1, Cond);
    return DAG.getNode(X86ISD::SELECTS, DL, VT, Cmp, Op1, Op2);
  }


Repository:
  rL LLVM

https://reviews.llvm.org/D47012