[llvm] r333158 - [RISCV] Support linker relax function call from auipc and jalr to jal
Shiva Chen via llvm-commits
llvm-commits at lists.llvm.org
Wed May 23 23:21:24 PDT 2018
Author: shiva
Date: Wed May 23 23:21:23 2018
New Revision: 333158
URL: http://llvm.org/viewvc/llvm-project?rev=333158&view=rev
Log:
[RISCV] Support linker relax function call from auipc and jalr to jal
To do this:
1. Add fixup_riscv_relax fixup types which eventually will
transfer to R_RISCV_RELAX relocation types.
2. Insert R_RISCV_RELAX relocation types to auipc function call
expression when linker relaxation enabled.
Differential Revision: https://reviews.llvm.org/D44886
Added:
llvm/trunk/test/MC/RISCV/linker-relaxation.s
Modified:
llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
Modified: llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp?rev=333158&r1=333157&r2=333158&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp Wed May 23 23:21:23 2018
@@ -88,7 +88,8 @@ public:
{ "fixup_riscv_jal", 12, 20, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_riscv_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_riscv_rvc_jump", 2, 11, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_riscv_rvc_branch", 0, 16, MCFixupKindInfo::FKF_IsPCRel }
+ { "fixup_riscv_rvc_branch", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_riscv_relax", 0, 0, 0 }
};
if (Kind < FirstTargetFixupKind)
Modified: llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp?rev=333158&r1=333157&r2=333158&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp Wed May 23 23:21:23 2018
@@ -94,6 +94,8 @@ unsigned RISCVELFObjectWriter::getRelocT
return ELF::R_RISCV_RVC_BRANCH;
case RISCV::fixup_riscv_call:
return ELF::R_RISCV_CALL;
+ case RISCV::fixup_riscv_relax:
+ return ELF::R_RISCV_RELAX;
}
}
Modified: llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h?rev=333158&r1=333157&r2=333158&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h (original)
+++ llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h Wed May 23 23:21:23 2018
@@ -50,6 +50,9 @@ enum Fixups {
// fixup_riscv_call - A fixup representing a call attached to the auipc
// instruction in a pair composed of adjacent auipc+jalr instructions.
fixup_riscv_call,
+ // fixup_riscv_relax - Used to generate an R_RISCV_RELAX relocation type,
+ // which indicates the linker may relax the instruction pair.
+ fixup_riscv_relax,
// fixup_riscv_invalid - used as a sentinel and a marker, must be last fixup
fixup_riscv_invalid,
Modified: llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp?rev=333158&r1=333157&r2=333158&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp Wed May 23 23:21:23 2018
@@ -186,7 +186,7 @@ RISCVMCCodeEmitter::getImmOpValueAsr1(co
unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
-
+ bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax];
const MCOperand &MO = MI.getOperand(OpNo);
MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
@@ -254,6 +254,15 @@ unsigned RISCVMCCodeEmitter::getImmOpVal
MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
++MCNumFixups;
+ if (EnableRelax) {
+ if (FixupKind == RISCV::fixup_riscv_call) {
+ Fixups.push_back(
+ MCFixup::create(0, Expr, MCFixupKind(RISCV::fixup_riscv_relax),
+ MI.getLoc()));
+ ++MCNumFixups;
+ }
+ }
+
return 0;
}
Added: llvm/trunk/test/MC/RISCV/linker-relaxation.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/linker-relaxation.s?rev=333158&view=auto
==============================================================================
--- llvm/trunk/test/MC/RISCV/linker-relaxation.s (added)
+++ llvm/trunk/test/MC/RISCV/linker-relaxation.s Wed May 23 23:21:23 2018
@@ -0,0 +1,26 @@
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+relax < %s \
+# RUN: | llvm-readobj -r | FileCheck -check-prefix=RELAX-RELOC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-relax < %s \
+# RUN: | llvm-readobj -r | FileCheck -check-prefix=NORELAX-RELOC %s
+# RUN: llvm-mc -triple riscv32 -mattr=+relax < %s -show-encoding \
+# RUN: | FileCheck -check-prefix=RELAX-FIXUP %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+relax < %s \
+# RUN: | llvm-readobj -r | FileCheck -check-prefix=RELAX-RELOC %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-relax < %s \
+# RUN: | llvm-readobj -r | FileCheck -check-prefix=NORELAX-RELOC %s
+# RUN: llvm-mc -triple riscv64 -mattr=+relax < %s -show-encoding \
+# RUN: | FileCheck -check-prefix=RELAX-FIXUP %s
+
+.long foo
+
+.L1:
+call foo
+# NORELAX-RELOC: R_RISCV_CALL foo 0x0
+# NORELAX-RELOC-NOT: R_RISCV_RELAX
+# RELAX-RELOC: R_RISCV_CALL foo 0x0
+# RELAX-RELOC: R_RISCV_RELAX foo 0x0
+# RELAX-FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_relax
+# RELAX-FIXUP: fixup B - offset: 0, value: foo, kind:
+beq s1, s1, .L1
+# RELAX-RELOC: R_RISCV_BRANCH .L1 0x0
+# RELAX-FIXUP: fixup A - offset: 0, value: .L1, kind: fixup_riscv_branch
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