[PATCH] D45395: [RISCV] Lower the tail pseudoinstruction

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

I'm not sure what I did wrong when first trying PseudoInstExpansion with PseudoTailIndirect, but I'm not seeing any problems now. Replace the current PseudoTAILIndirect definition with the following and drop the RISCVAsmPrinter changes:

  def PseudoTAILIndirect : Pseudo<(outs), (ins GPRTC:$rs1), [(Tail GPRTC:$rs1)]>,
                           PseudoInstExpansion<(JALR X0, GPR:$rs1, 0)>;

This generates the following in RISCVGenMCPseudoLowering.inc:

  case RISCV::PseudoTAILIndirect: {
    MCInst TmpInst;
    MCOperand MCOp;
    TmpInst.setOpcode(RISCV::JALR);
    // Operand: rd
    TmpInst.addOperand(MCOperand::createReg(RISCV::X0));
    // Operand: rs1
    lowerOperand(MI->getOperand(0), MCOp);
    TmpInst.addOperand(MCOp);
    // Operand: imm12
    TmpInst.addOperand(MCOperand::createImm(0));
    EmitToStreamer(OutStreamer, TmpInst);
    break;
  }

With that change, this looks good to me.


https://reviews.llvm.org/D45395