[PATCH] D43982: [GlobalISel][ARM] Adding HPR and QPR regclasses to FPRB regbank

[Roman Tereshin via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL333056: [GlobalISel][ARM] Adding HPR and QPR regclasses to FPRB regbank (authored by rtereshin, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D43982?vs=147236&id=148150#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D43982

Files:
  llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
  llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
  llvm/trunk/lib/Target/ARM/ARMRegisterBanks.td


Index: llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
+++ llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -134,6 +134,8 @@
       return &ARM::SPRRegClass;
     else if (Size == 64)
       return &ARM::DPRRegClass;
+    else if (Size == 128)
+      return &ARM::QPRRegClass;
     else
       llvm_unreachable("Unsupported destination size");
   }
Index: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -175,15 +175,20 @@
 
   switch (RC.getID()) {
   case GPRRegClassID:
+  case GPRwithAPSRRegClassID:
   case GPRnopcRegClassID:
+  case rGPRRegClassID:
   case GPRspRegClassID:
   case tGPR_and_tcGPRRegClassID:
+  case tcGPRRegClassID:
   case tGPRRegClassID:
     return getRegBank(ARM::GPRRegBankID);
+  case HPRRegClassID:
   case SPR_8RegClassID:
   case SPRRegClassID:
   case DPR_8RegClassID:
   case DPRRegClassID:
+  case QPRRegClassID:
     return getRegBank(ARM::FPRRegBankID);
   default:
     llvm_unreachable("Unsupported register kind");
Index: llvm/trunk/lib/Target/ARM/ARMRegisterBanks.td
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBanks.td
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBanks.td
@@ -11,4 +11,4 @@
 //===----------------------------------------------------------------------===//
 
 def GPRRegBank : RegisterBank<"GPRB", [GPR, GPRwithAPSR]>;
-def FPRRegBank : RegisterBank<"FPRB", [SPR, DPR]>;
+def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;


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