[llvm] r333056 - [GlobalISel][ARM] Adding HPR and QPR regclasses to FPRB regbank

[Roman Tereshin via llvm-commits]

Author: rtereshin
Date: Tue May 22 19:59:31 2018
New Revision: 333056

URL: http://llvm.org/viewvc/llvm-project?rev=333056&view=rev
Log:
[GlobalISel][ARM] Adding HPR and QPR regclasses to FPRB regbank

Also bringing ARMRegisterBankInfo::getRegBankFromRegClass
implementation up to speed with the *.td-definition.

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D43982

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
    llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMRegisterBanks.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp?rev=333056&r1=333055&r2=333056&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp Tue May 22 19:59:31 2018
@@ -134,6 +134,8 @@ static const TargetRegisterClass *guessR
       return &ARM::SPRRegClass;
     else if (Size == 64)
       return &ARM::DPRRegClass;
+    else if (Size == 128)
+      return &ARM::QPRRegClass;
     else
       llvm_unreachable("Unsupported destination size");
   }

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=333056&r1=333055&r2=333056&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Tue May 22 19:59:31 2018
@@ -175,15 +175,20 @@ const RegisterBank &ARMRegisterBankInfo:
 
   switch (RC.getID()) {
   case GPRRegClassID:
+  case GPRwithAPSRRegClassID:
   case GPRnopcRegClassID:
+  case rGPRRegClassID:
   case GPRspRegClassID:
   case tGPR_and_tcGPRRegClassID:
+  case tcGPRRegClassID:
   case tGPRRegClassID:
     return getRegBank(ARM::GPRRegBankID);
+  case HPRRegClassID:
   case SPR_8RegClassID:
   case SPRRegClassID:
   case DPR_8RegClassID:
   case DPRRegClassID:
+  case QPRRegClassID:
     return getRegBank(ARM::FPRRegBankID);
   default:
     llvm_unreachable("Unsupported register kind");

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBanks.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBanks.td?rev=333056&r1=333055&r2=333056&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBanks.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBanks.td Tue May 22 19:59:31 2018
@@ -11,4 +11,4 @@
 //===----------------------------------------------------------------------===//
 
 def GPRRegBank : RegisterBank<"GPRB", [GPR, GPRwithAPSR]>;
-def FPRRegBank : RegisterBank<"FPRB", [SPR, DPR]>;
+def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;