[llvm] r332857 - MC: Change MCAsmBackend::writeNopData() to take a raw_ostream instead of an MCObjectWriter. NFCI.
Peter Collingbourne via llvm-commits
llvm-commits at lists.llvm.org
Mon May 21 10:57:20 PDT 2018
Author: pcc
Date: Mon May 21 10:57:19 2018
New Revision: 332857
URL: http://llvm.org/viewvc/llvm-project?rev=332857&view=rev
Log:
MC: Change MCAsmBackend::writeNopData() to take a raw_ostream instead of an MCObjectWriter. NFCI.
To make this work I needed to add an endianness field to MCAsmBackend
so that writeNopData() implementations know which endianness to use.
Part of PR37466.
Differential Revision: https://reviews.llvm.org/D47035
Modified:
llvm/trunk/include/llvm/MC/MCAsmBackend.h
llvm/trunk/lib/MC/MCAsmBackend.cpp
llvm/trunk/lib/MC/MCAssembler.cpp
llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h
llvm/trunk/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
llvm/trunk/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h
llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2AsmBackend.cpp
llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2AsmBackend.h
llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp
llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
Modified: llvm/trunk/include/llvm/MC/MCAsmBackend.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmBackend.h?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAsmBackend.h (original)
+++ llvm/trunk/include/llvm/MC/MCAsmBackend.h Mon May 21 10:57:19 2018
@@ -16,6 +16,7 @@
#include "llvm/MC/MCDirectives.h"
#include "llvm/MC/MCFixup.h"
#include "llvm/MC/MCFragment.h"
+#include "llvm/Support/Endian.h"
#include <cstdint>
#include <memory>
@@ -41,14 +42,15 @@ class MCAsmBackend {
std::unique_ptr<MCCodePadder> CodePadder;
protected: // Can only create subclasses.
- MCAsmBackend();
- MCAsmBackend(std::unique_ptr<MCCodePadder> TargetCodePadder);
+ MCAsmBackend(support::endianness Endian);
public:
MCAsmBackend(const MCAsmBackend &) = delete;
MCAsmBackend &operator=(const MCAsmBackend &) = delete;
virtual ~MCAsmBackend();
+ const support::endianness Endian;
+
/// lifetime management
virtual void reset() {}
@@ -128,7 +130,7 @@ public:
/// target cannot generate such a sequence, it should return an error.
///
/// \return - True on success.
- virtual bool writeNopData(uint64_t Count, MCObjectWriter *OW) const = 0;
+ virtual bool writeNopData(raw_ostream &OS, uint64_t Count) const = 0;
/// Give backend an opportunity to finish layout after relaxation
virtual void finishLayout(MCAssembler const &Asm,
Modified: llvm/trunk/lib/MC/MCAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmBackend.cpp?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmBackend.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmBackend.cpp Mon May 21 10:57:19 2018
@@ -18,10 +18,8 @@
using namespace llvm;
-MCAsmBackend::MCAsmBackend() : CodePadder(new MCCodePadder()) {}
-
-MCAsmBackend::MCAsmBackend(std::unique_ptr<MCCodePadder> TargetCodePadder)
- : CodePadder(std::move(TargetCodePadder)) {}
+MCAsmBackend::MCAsmBackend(support::endianness Endian)
+ : CodePadder(new MCCodePadder()), Endian(Endian) {}
MCAsmBackend::~MCAsmBackend() = default;
Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Mon May 21 10:57:19 2018
@@ -472,12 +472,12 @@ void MCAssembler::writeFragmentPadding(c
// ----------------------------
// ^-------------------^ <- TotalLength
unsigned DistanceToBoundary = TotalLength - getBundleAlignSize();
- if (!getBackend().writeNopData(DistanceToBoundary, OW))
+ if (!getBackend().writeNopData(OW->getStream(), DistanceToBoundary))
report_fatal_error("unable to write NOP sequence of " +
Twine(DistanceToBoundary) + " bytes");
BundlePadding -= DistanceToBoundary;
}
- if (!getBackend().writeNopData(BundlePadding, OW))
+ if (!getBackend().writeNopData(OW->getStream(), BundlePadding))
report_fatal_error("unable to write NOP sequence of " +
Twine(BundlePadding) + " bytes");
}
@@ -523,7 +523,7 @@ static void writeFragment(const MCAssemb
// bytes left to fill use the Value and ValueSize to fill the rest.
// If we are aligning with nops, ask that target to emit the right data.
if (AF.hasEmitNops()) {
- if (!Asm.getBackend().writeNopData(Count, OW))
+ if (!Asm.getBackend().writeNopData(OW->getStream(), Count))
report_fatal_error("unable to write nop sequence of " +
Twine(Count) + " bytes");
break;
@@ -600,7 +600,7 @@ static void writeFragment(const MCAssemb
}
case MCFragment::FT_Padding: {
- if (!Asm.getBackend().writeNopData(FragmentSize, OW))
+ if (!Asm.getBackend().writeNopData(OW->getStream(), FragmentSize))
report_fatal_error("unable to write nop sequence of " +
Twine(FragmentSize) + " bytes");
break;
Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp Mon May 21 10:57:19 2018
@@ -33,11 +33,9 @@ class AArch64AsmBackend : public MCAsmBa
Triple TheTriple;
public:
- bool IsLittleEndian;
-
-public:
AArch64AsmBackend(const Target &T, const Triple &TT, bool IsLittleEndian)
- : MCAsmBackend(), TheTriple(TT), IsLittleEndian(IsLittleEndian) {}
+ : MCAsmBackend(IsLittleEndian ? support::little : support::big),
+ TheTriple(TT) {}
unsigned getNumFixupKinds() const override {
return AArch64::NumTargetFixupKinds;
@@ -83,7 +81,7 @@ public:
const MCAsmLayout &Layout) const override;
void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
MCInst &Res) const override;
- bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+ bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
void HandleAssemblerFlag(MCAssemblerFlag Flag) {}
@@ -248,7 +246,7 @@ static uint64_t adjustFixupValue(const M
/// getFixupKindContainereSizeInBytes - The number of bytes of the
/// container involved in big endian or 0 if the item is little endian
unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(unsigned Kind) const {
- if (IsLittleEndian)
+ if (Endian == support::little)
return 0;
switch (Kind) {
@@ -344,16 +342,16 @@ void AArch64AsmBackend::relaxInstruction
llvm_unreachable("AArch64AsmBackend::relaxInstruction() unimplemented");
}
-bool AArch64AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+bool AArch64AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
// If the count is not 4-byte aligned, we must be writing data into the text
// section (otherwise we have unaligned instructions, and thus have far
// bigger problems), so just write zeros instead.
- OW->WriteZeros(Count % 4);
+ OS.write_zeros(Count % 4);
// We are properly aligned, so write NOPs as requested.
Count /= 4;
for (uint64_t i = 0; i != Count; ++i)
- OW->write32(0xd503201f);
+ support::endian::write<uint32_t>(OS, 0xd503201f, Endian);
return true;
}
@@ -585,7 +583,8 @@ public:
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override {
- return createAArch64ELFObjectWriter(OS, OSABI, IsLittleEndian, IsILP32);
+ return createAArch64ELFObjectWriter(OS, OSABI,
+ Endian == support::little, IsILP32);
}
};
Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp Mon May 21 10:57:19 2018
@@ -26,8 +26,7 @@ namespace {
class AMDGPUAsmBackend : public MCAsmBackend {
public:
- AMDGPUAsmBackend(const Target &T)
- : MCAsmBackend() {}
+ AMDGPUAsmBackend(const Target &T) : MCAsmBackend(support::little) {}
unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; };
@@ -46,7 +45,7 @@ public:
bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
unsigned getMinimumNopSize() const override;
- bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+ bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
};
@@ -140,11 +139,11 @@ unsigned AMDGPUAsmBackend::getMinimumNop
return 4;
}
-bool AMDGPUAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+bool AMDGPUAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
// If the count is not 4-byte aligned, we must be writing data into the text
// section (otherwise we have unaligned instructions, and thus have far
// bigger problems), so just write zeros instead.
- OW->WriteZeros(Count % 4);
+ OS.write_zeros(Count % 4);
// We are properly aligned, so write NOPs as requested.
Count /= 4;
@@ -154,7 +153,7 @@ bool AMDGPUAsmBackend::writeNopData(uint
const uint32_t Encoded_S_NOP_0 = 0xbf800000;
for (uint64_t I = 0; I != Count; ++I)
- OW->write32(Encoded_S_NOP_0);
+ support::endian::write<uint32_t>(OS, Encoded_S_NOP_0, Endian);
return true;
}
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Mon May 21 10:57:19 2018
@@ -31,6 +31,7 @@
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCValue.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/EndianStream.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/TargetParser.h"
@@ -155,7 +156,8 @@ const MCFixupKindInfo &ARMAsmBackend::ge
assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
"Invalid kind!");
- return (IsLittleEndian ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind];
+ return (Endian == support::little ? InfosLE
+ : InfosBE)[Kind - FirstTargetFixupKind];
}
void ARMAsmBackend::handleAssemblerFlag(MCAssemblerFlag Flag) {
@@ -289,7 +291,7 @@ void ARMAsmBackend::relaxInstruction(con
Res.setOpcode(RelaxedOp);
}
-bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+bool ARMAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0
@@ -299,9 +301,9 @@ bool ARMAsmBackend::writeNopData(uint64_
hasNOP() ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
uint64_t NumNops = Count / 2;
for (uint64_t i = 0; i != NumNops; ++i)
- OW->write16(nopEncoding);
+ support::endian::write(OS, nopEncoding, Endian);
if (Count & 1)
- OW->write8(0);
+ OS << '\0';
return true;
}
// ARM mode
@@ -309,21 +311,20 @@ bool ARMAsmBackend::writeNopData(uint64_
hasNOP() ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
uint64_t NumNops = Count / 4;
for (uint64_t i = 0; i != NumNops; ++i)
- OW->write32(nopEncoding);
+ support::endian::write(OS, nopEncoding, Endian);
// FIXME: should this function return false when unable to write exactly
// 'Count' bytes with NOP encodings?
switch (Count % 4) {
default:
break; // No leftover bytes to write
case 1:
- OW->write8(0);
+ OS << '\0';
break;
case 2:
- OW->write16(0);
+ OS.write("\0\0", 2);
break;
case 3:
- OW->write16(0);
- OW->write8(0xa0);
+ OS.write("\0\0\xa0", 3);
break;
}
@@ -413,7 +414,7 @@ unsigned ARMAsmBackend::adjustFixupValue
// inst{14-12} = Mid3;
// inst{7-0} = Lo8;
Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
- return swapHalfWords(Value, IsLittleEndian);
+ return swapHalfWords(Value, Endian == support::little);
}
case ARM::fixup_arm_ldst_pcrel_12:
// ARM PC-relative values are offset by 8.
@@ -436,7 +437,7 @@ unsigned ARMAsmBackend::adjustFixupValue
// Same addressing mode as fixup_arm_pcrel_10,
// but with 16-bit halfwords swapped.
if (Kind == ARM::fixup_t2_ldst_pcrel_12)
- return swapHalfWords(Value, IsLittleEndian);
+ return swapHalfWords(Value, Endian == support::little);
return Value;
}
@@ -469,7 +470,7 @@ unsigned ARMAsmBackend::adjustFixupValue
out |= (Value & 0x700) << 4;
out |= (Value & 0x0FF);
- return swapHalfWords(out, IsLittleEndian);
+ return swapHalfWords(out, Endian == support::little);
}
case ARM::fixup_arm_condbranch:
@@ -501,7 +502,7 @@ unsigned ARMAsmBackend::adjustFixupValue
out |= (Value & 0x1FF800) << 5; // imm6 field
out |= (Value & 0x0007FF); // imm11 field
- return swapHalfWords(out, IsLittleEndian);
+ return swapHalfWords(out, Endian == support::little);
}
case ARM::fixup_t2_condbranch: {
Value = Value - 4;
@@ -514,7 +515,7 @@ unsigned ARMAsmBackend::adjustFixupValue
out |= (Value & 0x1F800) << 5; // imm6 field
out |= (Value & 0x007FF); // imm11 field
- return swapHalfWords(out, IsLittleEndian);
+ return swapHalfWords(out, Endian == support::little);
}
case ARM::fixup_arm_thumb_bl: {
// FIXME: We get both thumb1 and thumb2 in here, so we can only check for
@@ -548,7 +549,7 @@ unsigned ARMAsmBackend::adjustFixupValue
uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
(uint16_t)imm11Bits);
- return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian);
+ return joinHalfWords(FirstHalf, SecondHalf, Endian == support::little);
}
case ARM::fixup_arm_thumb_blx: {
// The value doesn't encode the low two bits (always zero) and is offset by
@@ -584,7 +585,7 @@ unsigned ARMAsmBackend::adjustFixupValue
uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
((uint16_t)imm10LBits) << 1);
- return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian);
+ return joinHalfWords(FirstHalf, SecondHalf, Endian == support::little);
}
case ARM::fixup_thumb_adr_pcrel_10:
case ARM::fixup_arm_thumb_cp:
@@ -672,7 +673,7 @@ unsigned ARMAsmBackend::adjustFixupValue
// Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
// swapped.
if (Kind == ARM::fixup_t2_pcrel_10)
- return swapHalfWords(Value, IsLittleEndian);
+ return swapHalfWords(Value, Endian == support::little);
return Value;
}
@@ -703,7 +704,7 @@ unsigned ARMAsmBackend::adjustFixupValue
// Same addressing mode as fixup_arm_pcrel_9, but with 16-bit halfwords
// swapped.
if (Kind == ARM::fixup_t2_pcrel_9)
- return swapHalfWords(Value, IsLittleEndian);
+ return swapHalfWords(Value, Endian == support::little);
return Value;
}
@@ -729,7 +730,7 @@ unsigned ARMAsmBackend::adjustFixupValue
EncValue |= (Value & 0x800) << 15;
EncValue |= (Value & 0x700) << 4;
EncValue |= (Value & 0xff);
- return swapHalfWords(EncValue, IsLittleEndian);
+ return swapHalfWords(EncValue, Endian == support::little);
}
}
}
@@ -893,7 +894,7 @@ void ARMAsmBackend::applyFixup(const MCA
// Used to point to big endian bytes.
unsigned FullSizeBytes;
- if (!IsLittleEndian) {
+ if (Endian == support::big) {
FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind());
assert((Offset + FullSizeBytes) <= Data.size() && "Invalid fixup size!");
assert(NumBytes <= FullSizeBytes && "Invalid fixup size!");
@@ -903,7 +904,7 @@ void ARMAsmBackend::applyFixup(const MCA
// the fixup value. The Value has been "split up" into the appropriate
// bitfields above.
for (unsigned i = 0; i != NumBytes; ++i) {
- unsigned Idx = IsLittleEndian ? i : (FullSizeBytes - 1 - i);
+ unsigned Idx = Endian == support::little ? i : (FullSizeBytes - 1 - i);
Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
}
}
@@ -1155,7 +1156,7 @@ static MCAsmBackend *createARMAsmBackend
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI,
const MCTargetOptions &Options,
- bool isLittle) {
+ support::endianness Endian) {
const Triple &TheTriple = STI.getTargetTriple();
switch (TheTriple.getObjectFormat()) {
default:
@@ -1170,7 +1171,7 @@ static MCAsmBackend *createARMAsmBackend
case Triple::ELF:
assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
- return new ARMAsmBackendELF(T, STI, OSABI, isLittle);
+ return new ARMAsmBackendELF(T, STI, OSABI, Endian);
}
}
@@ -1178,12 +1179,12 @@ MCAsmBackend *llvm::createARMLEAsmBacken
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI,
const MCTargetOptions &Options) {
- return createARMAsmBackend(T, STI, MRI, Options, true);
+ return createARMAsmBackend(T, STI, MRI, Options, support::little);
}
MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI,
const MCTargetOptions &Options) {
- return createARMAsmBackend(T, STI, MRI, Options, false);
+ return createARMAsmBackend(T, STI, MRI, Options, support::big);
}
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h Mon May 21 10:57:19 2018
@@ -21,12 +21,11 @@ namespace llvm {
class ARMAsmBackend : public MCAsmBackend {
const MCSubtargetInfo &STI;
bool isThumbMode; // Currently emitting Thumb code.
- bool IsLittleEndian; // Big or little endian.
public:
- ARMAsmBackend(const Target &T, const MCSubtargetInfo &STI, bool IsLittle)
- : MCAsmBackend(), STI(STI),
- isThumbMode(STI.getTargetTriple().isThumb()),
- IsLittleEndian(IsLittle) {}
+ ARMAsmBackend(const Target &T, const MCSubtargetInfo &STI,
+ support::endianness Endian)
+ : MCAsmBackend(Endian), STI(STI),
+ isThumbMode(STI.getTargetTriple().isThumb()) {}
unsigned getNumFixupKinds() const override {
return ARM::NumTargetFixupKinds;
@@ -61,14 +60,13 @@ public:
void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
MCInst &Res) const override;
- bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+ bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
void handleAssemblerFlag(MCAssemblerFlag Flag) override;
unsigned getPointerSize() const { return 4; }
bool isThumb() const { return isThumbMode; }
void setIsThumb(bool it) { isThumbMode = it; }
- bool isLittle() const { return IsLittleEndian; }
};
} // end namespace llvm
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h Mon May 21 10:57:19 2018
@@ -21,8 +21,7 @@ public:
const MachO::CPUSubTypeARM Subtype;
ARMAsmBackendDarwin(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, MachO::CPUSubTypeARM st)
- : ARMAsmBackend(T, STI, /* IsLittleEndian */ true), MRI(MRI),
- Subtype(st) {}
+ : ARMAsmBackend(T, STI, support::little), MRI(MRI), Subtype(st) {}
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override {
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h Mon May 21 10:57:19 2018
@@ -21,12 +21,12 @@ class ARMAsmBackendELF : public ARMAsmBa
public:
uint8_t OSABI;
ARMAsmBackendELF(const Target &T, const MCSubtargetInfo &STI, uint8_t OSABI,
- bool IsLittle)
- : ARMAsmBackend(T, STI, IsLittle), OSABI(OSABI) {}
+ support::endianness Endian)
+ : ARMAsmBackend(T, STI, Endian), OSABI(OSABI) {}
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override {
- return createARMELFObjectWriter(OS, OSABI, isLittle());
+ return createARMELFObjectWriter(OS, OSABI, Endian);
}
};
}
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h Mon May 21 10:57:19 2018
@@ -18,7 +18,7 @@ namespace {
class ARMAsmBackendWinCOFF : public ARMAsmBackend {
public:
ARMAsmBackendWinCOFF(const Target &T, const MCSubtargetInfo &STI)
- : ARMAsmBackend(T, STI, true) {}
+ : ARMAsmBackend(T, STI, support::little) {}
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override {
return createARMWinCOFFObjectWriter(OS, /*Is64Bit=*/false);
Modified: llvm/trunk/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp Mon May 21 10:57:19 2018
@@ -453,13 +453,13 @@ MCFixupKindInfo const &AVRAsmBackend::ge
return Infos[Kind - FirstTargetFixupKind];
}
-bool AVRAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+bool AVRAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
// If the count is not 2-byte aligned, we must be writing data into the text
// section (otherwise we have unaligned instructions, and thus have far
// bigger problems), so just write zeros instead.
assert((Count % 2) == 0 && "NOP instructions must be 2 bytes");
- OW->WriteZeros(Count);
+ OS.write_zeros(Count);
return true;
}
Modified: llvm/trunk/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h (original)
+++ llvm/trunk/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h Mon May 21 10:57:19 2018
@@ -31,9 +31,8 @@ struct MCFixupKindInfo;
/// Utilities for manipulating generated AVR machine code.
class AVRAsmBackend : public MCAsmBackend {
public:
-
AVRAsmBackend(Triple::OSType OSType)
- : MCAsmBackend(), OSType(OSType) {}
+ : MCAsmBackend(support::little), OSType(OSType) {}
void adjustFixupValue(const MCFixup &Fixup, const MCValue &Target,
uint64_t &Value, MCContext *Ctx = nullptr) const;
@@ -62,7 +61,7 @@ public:
void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
MCInst &Res) const override {}
- bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+ bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
const MCValue &Target) override;
Modified: llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp Mon May 21 10:57:19 2018
@@ -12,6 +12,7 @@
#include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCFixup.h"
#include "llvm/MC/MCObjectWriter.h"
+#include "llvm/Support/EndianStream.h"
#include <cassert>
#include <cstdint>
@@ -21,10 +22,7 @@ namespace {
class BPFAsmBackend : public MCAsmBackend {
public:
- bool IsLittleEndian;
-
- BPFAsmBackend(bool IsLittleEndian)
- : MCAsmBackend(), IsLittleEndian(IsLittleEndian) {}
+ BPFAsmBackend(support::endianness Endian) : MCAsmBackend(Endian) {}
~BPFAsmBackend() override = default;
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
@@ -48,17 +46,17 @@ public:
void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
MCInst &Res) const override {}
- bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+ bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
};
} // end anonymous namespace
-bool BPFAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+bool BPFAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
if ((Count % 8) != 0)
return false;
for (uint64_t i = 0; i < Count; i += 8)
- OW->write64(0x15000000);
+ support::endian::write<uint64_t>(OS, 0x15000000, Endian);
return true;
}
@@ -69,16 +67,13 @@ void BPFAsmBackend::applyFixup(const MCA
bool IsResolved) const {
if (Fixup.getKind() == FK_SecRel_4 || Fixup.getKind() == FK_SecRel_8) {
assert(Value == 0);
- } else if (Fixup.getKind() == FK_Data_4 || Fixup.getKind() == FK_Data_8) {
- unsigned Size = Fixup.getKind() == FK_Data_4 ? 4 : 8;
-
- for (unsigned i = 0; i != Size; ++i) {
- unsigned Idx = IsLittleEndian ? i : Size - i - 1;
- Data[Fixup.getOffset() + Idx] = uint8_t(Value >> (i * 8));
- }
+ } else if (Fixup.getKind() == FK_Data_4) {
+ support::endian::write<uint32_t>(&Data[Fixup.getOffset()], Value, Endian);
+ } else if (Fixup.getKind() == FK_Data_8) {
+ support::endian::write<uint64_t>(&Data[Fixup.getOffset()], Value, Endian);
} else if (Fixup.getKind() == FK_PCRel_4) {
Value = (uint32_t)((Value - 8) / 8);
- if (IsLittleEndian) {
+ if (Endian == support::little) {
Data[Fixup.getOffset() + 1] = 0x10;
support::endian::write32le(&Data[Fixup.getOffset() + 4], Value);
} else {
@@ -88,31 +83,26 @@ void BPFAsmBackend::applyFixup(const MCA
} else {
assert(Fixup.getKind() == FK_PCRel_2);
Value = (uint16_t)((Value - 8) / 8);
- if (IsLittleEndian) {
- Data[Fixup.getOffset() + 2] = Value & 0xFF;
- Data[Fixup.getOffset() + 3] = Value >> 8;
- } else {
- Data[Fixup.getOffset() + 2] = Value >> 8;
- Data[Fixup.getOffset() + 3] = Value & 0xFF;
- }
+ support::endian::write<uint16_t>(&Data[Fixup.getOffset() + 2], Value,
+ Endian);
}
}
std::unique_ptr<MCObjectWriter>
BPFAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
- return createBPFELFObjectWriter(OS, 0, IsLittleEndian);
+ return createBPFELFObjectWriter(OS, 0, Endian == support::little);
}
MCAsmBackend *llvm::createBPFAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI,
const MCTargetOptions &) {
- return new BPFAsmBackend(/*IsLittleEndian=*/true);
+ return new BPFAsmBackend(support::little);
}
MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI,
const MCTargetOptions &) {
- return new BPFAsmBackend(/*IsLittleEndian=*/false);
+ return new BPFAsmBackend(support::big);
}
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp Mon May 21 10:57:19 2018
@@ -61,9 +61,10 @@ class HexagonAsmBackend : public MCAsmBa
public:
HexagonAsmBackend(const Target &T, const Triple &TT, uint8_t OSABI,
- StringRef CPU) :
- OSABI(OSABI), CPU(CPU), MCII(T.createMCInstrInfo()),
- RelaxTarget(new MCInst *), Extender(nullptr) {}
+ StringRef CPU)
+ : MCAsmBackend(support::little), OSABI(OSABI), CPU(CPU),
+ MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *),
+ Extender(nullptr) {}
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override {
@@ -681,8 +682,7 @@ public:
assert(Update && "Didn't find relaxation target");
}
- bool writeNopData(uint64_t Count,
- MCObjectWriter * OW) const override {
+ bool writeNopData(raw_ostream &OS, uint64_t Count) const override {
static const uint32_t Nopcode = 0x7f000000, // Hard-coded NOP.
ParseIn = 0x00004000, // In packet parse-bits.
ParseEnd = 0x0000c000; // End of packet parse-bits.
@@ -692,7 +692,7 @@ public:
<< Count % HEXAGON_INSTR_SIZE << "/"
<< HEXAGON_INSTR_SIZE << "\n");
--Count;
- OW->write8(0);
+ OS << '\0';
}
while(Count) {
@@ -700,7 +700,7 @@ public:
// Close the packet whenever a multiple of the maximum packet size remains
uint32_t ParseBits = (Count % (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE))?
ParseIn: ParseEnd;
- OW->write32(Nopcode | ParseBits);
+ support::endian::write<uint32_t>(OS, Nopcode | ParseBits, Endian);
}
return true;
}
Modified: llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp Mon May 21 10:57:19 2018
@@ -47,7 +47,7 @@ class LanaiAsmBackend : public MCAsmBack
public:
LanaiAsmBackend(const Target &T, Triple::OSType OST)
- : MCAsmBackend(), OSType(OST) {}
+ : MCAsmBackend(support::big), OSType(OST) {}
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
const MCValue &Target, MutableArrayRef<char> Data,
@@ -77,15 +77,15 @@ public:
const MCSubtargetInfo & /*STI*/,
MCInst & /*Res*/) const override {}
- bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+ bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
};
-bool LanaiAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+bool LanaiAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
if ((Count % 4) != 0)
return false;
for (uint64_t i = 0; i < Count; i += 4)
- OW->write32(0x15000000);
+ OS.write("\x15\0\0\0", 4);
return true;
}
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Mon May 21 10:57:19 2018
@@ -276,9 +276,9 @@ void MipsAsmBackend::applyFixup(const MC
bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind);
for (unsigned i = 0; i != NumBytes; ++i) {
- unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
- : i)
- : (FullSize - 1 - i);
+ unsigned Idx = Endian == support::little
+ ? (microMipsLEByteOrder ? calculateMMLEIndex(i) : i)
+ : (FullSize - 1 - i);
CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
}
@@ -288,9 +288,9 @@ void MipsAsmBackend::applyFixup(const MC
// Write out the fixed up bytes back to the code/data bits.
for (unsigned i = 0; i != NumBytes; ++i) {
- unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
- : i)
- : (FullSize - 1 - i);
+ unsigned Idx = Endian == support::little
+ ? (microMipsLEByteOrder ? calculateMMLEIndex(i) : i)
+ : (FullSize - 1 - i);
Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
}
}
@@ -458,7 +458,7 @@ getFixupKindInfo(MCFixupKind Kind) const
assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
"Invalid kind!");
- if (IsLittle)
+ if (Endian == support::little)
return LittleEndianInfos[Kind - FirstTargetFixupKind];
return BigEndianInfos[Kind - FirstTargetFixupKind];
}
@@ -468,7 +468,7 @@ getFixupKindInfo(MCFixupKind Kind) const
/// it should return an error.
///
/// \return - True on success.
-bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+bool MipsAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
// Check for a less than instruction size number of bytes
// FIXME: 16 bit instructions are not handled yet here.
// We shouldn't be using a hard coded number for instruction size.
@@ -476,7 +476,7 @@ bool MipsAsmBackend::writeNopData(uint64
// If the count is not 4-byte aligned, we must be writing data into the text
// section (otherwise we have unaligned instructions, and thus have far
// bigger problems), so just write zeros instead.
- OW->WriteZeros(Count);
+ OS.write_zeros(Count);
return true;
}
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h Mon May 21 10:57:19 2018
@@ -29,13 +29,13 @@ class Target;
class MipsAsmBackend : public MCAsmBackend {
Triple TheTriple;
- bool IsLittle; // Big or little endian
bool IsN32;
public:
MipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT,
StringRef CPU, bool N32)
- : TheTriple(TT), IsLittle(TT.isLittleEndian()), IsN32(N32) {}
+ : MCAsmBackend(TT.isLittleEndian() ? support::little : support::big),
+ TheTriple(TT), IsN32(N32) {}
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override;
@@ -83,7 +83,7 @@ public:
/// @}
- bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+ bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
}; // class MipsAsmBackend
Modified: llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2AsmBackend.cpp?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2AsmBackend.cpp Mon May 21 10:57:19 2018
@@ -118,7 +118,7 @@ Nios2AsmBackend::createObjectWriter(raw_
MCELFObjectTargetWriter::getOSABI(OSType));
}
-bool Nios2AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+bool Nios2AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
return true;
}
Modified: llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2AsmBackend.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2AsmBackend.h?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2AsmBackend.h (original)
+++ llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2AsmBackend.h Mon May 21 10:57:19 2018
@@ -31,12 +31,12 @@ class Nios2AsmBackend : public MCAsmBack
public:
Nios2AsmBackend(const Target &T, Triple::OSType OSType)
- : MCAsmBackend(), OSType(OSType) {}
+ : MCAsmBackend(support::little), OSType(OSType) {}
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override;
- bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+ bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
const MCValue &Target, MutableArrayRef<char> Data,
Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp Mon May 21 10:57:19 2018
@@ -75,10 +75,9 @@ namespace {
class PPCAsmBackend : public MCAsmBackend {
const Target &TheTarget;
- bool IsLittleEndian;
public:
- PPCAsmBackend(const Target &T, bool isLittle) : MCAsmBackend(), TheTarget(T),
- IsLittleEndian(isLittle) {}
+ PPCAsmBackend(const Target &T, support::endianness Endian)
+ : MCAsmBackend(Endian), TheTarget(T) {}
unsigned getNumFixupKinds() const override {
return PPC::NumTargetFixupKinds;
@@ -111,7 +110,9 @@ public:
assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
"Invalid kind!");
- return (IsLittleEndian? InfosLE : InfosBE)[Kind - FirstTargetFixupKind];
+ return (Endian == support::little
+ ? InfosLE
+ : InfosBE)[Kind - FirstTargetFixupKind];
}
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
@@ -127,7 +128,7 @@ public:
// from the fixup value. The Value has been "split up" into the appropriate
// bitfields above.
for (unsigned i = 0; i != NumBytes; ++i) {
- unsigned Idx = IsLittleEndian ? i : (NumBytes - 1 - i);
+ unsigned Idx = Endian == support::little ? i : (NumBytes - 1 - i);
Data[Offset + i] |= uint8_t((Value >> (Idx * 8)) & 0xff);
}
}
@@ -175,12 +176,12 @@ public:
llvm_unreachable("relaxInstruction() unimplemented");
}
- bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
+ bool writeNopData(raw_ostream &OS, uint64_t Count) const override {
uint64_t NumNops = Count / 4;
for (uint64_t i = 0; i != NumNops; ++i)
- OW->write32(0x60000000);
+ support::endian::write<uint32_t>(OS, 0x60000000, Endian);
- OW->WriteZeros(Count % 4);
+ OS.write_zeros(Count % 4);
return true;
}
@@ -191,10 +192,6 @@ public:
assert(Name == "ppc32" && "Unknown target name!");
return 4;
}
-
- bool isLittleEndian() const {
- return IsLittleEndian;
- }
};
} // end anonymous namespace
@@ -203,7 +200,7 @@ public:
namespace {
class DarwinPPCAsmBackend : public PPCAsmBackend {
public:
- DarwinPPCAsmBackend(const Target &T) : PPCAsmBackend(T, false) { }
+ DarwinPPCAsmBackend(const Target &T) : PPCAsmBackend(T, support::big) { }
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override {
@@ -219,13 +216,15 @@ namespace {
class ELFPPCAsmBackend : public PPCAsmBackend {
uint8_t OSABI;
public:
- ELFPPCAsmBackend(const Target &T, bool IsLittleEndian, uint8_t OSABI) :
- PPCAsmBackend(T, IsLittleEndian), OSABI(OSABI) { }
+ ELFPPCAsmBackend(const Target &T, support::endianness Endian,
+ uint8_t OSABI)
+ : PPCAsmBackend(T, Endian), OSABI(OSABI) {}
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override {
bool is64 = getPointerSize() == 8;
- return createPPCELFObjectWriter(OS, is64, isLittleEndian(), OSABI);
+ return createPPCELFObjectWriter(OS, is64, Endian == support::little,
+ OSABI);
}
};
@@ -241,5 +240,6 @@ MCAsmBackend *llvm::createPPCAsmBackend(
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
bool IsLittleEndian = TT.getArch() == Triple::ppc64le;
- return new ELFPPCAsmBackend(T, IsLittleEndian, OSABI);
+ return new ELFPPCAsmBackend(
+ T, IsLittleEndian ? support::little : support::big, OSABI);
}
Modified: llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp Mon May 21 10:57:19 2018
@@ -33,7 +33,8 @@ class RISCVAsmBackend : public MCAsmBack
public:
RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit)
- : MCAsmBackend(), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit) {}
+ : MCAsmBackend(support::little), STI(STI), OSABI(OSABI),
+ Is64Bit(Is64Bit) {}
~RISCVAsmBackend() override {}
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
@@ -100,7 +101,7 @@ public:
MCInst &Res) const override;
- bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+ bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
};
@@ -188,7 +189,7 @@ bool RISCVAsmBackend::mayNeedRelaxation(
return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
}
-bool RISCVAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC];
unsigned MinNopLen = HasStdExtC ? 2 : 4;
@@ -198,13 +199,13 @@ bool RISCVAsmBackend::writeNopData(uint6
// The canonical nop on RISC-V is addi x0, x0, 0.
uint64_t Nop32Count = Count / 4;
for (uint64_t i = Nop32Count; i != 0; --i)
- OW->write32(0x13);
+ OS.write("\x13\0\0\0", 4);
// The canonical nop on RVC is c.nop.
if (HasStdExtC) {
uint64_t Nop16Count = (Count - Nop32Count * 4) / 2;
for (uint64_t i = Nop16Count; i != 0; --i)
- OW->write16(0x01);
+ OS.write("\x01\0", 2);
}
return true;
Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp Mon May 21 10:57:19 2018
@@ -100,14 +100,13 @@ namespace {
class SparcAsmBackend : public MCAsmBackend {
protected:
const Target &TheTarget;
- bool IsLittleEndian;
bool Is64Bit;
public:
SparcAsmBackend(const Target &T)
- : MCAsmBackend(), TheTarget(T),
- IsLittleEndian(StringRef(TheTarget.getName()) == "sparcel"),
- Is64Bit(StringRef(TheTarget.getName()) == "sparcv9") {}
+ : MCAsmBackend(StringRef(T.getName()) == "sparcel" ? support::little
+ : support::big),
+ TheTarget(T), Is64Bit(StringRef(TheTarget.getName()) == "sparcv9") {}
unsigned getNumFixupKinds() const override {
return Sparc::NumTargetFixupKinds;
@@ -197,7 +196,7 @@ namespace {
assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
"Invalid kind!");
- if (IsLittleEndian)
+ if (Endian == support::little)
return InfosLE[Kind - FirstTargetFixupKind];
return InfosBE[Kind - FirstTargetFixupKind];
@@ -255,14 +254,14 @@ namespace {
llvm_unreachable("relaxInstruction() unimplemented");
}
- bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
+ bool writeNopData(raw_ostream &OS, uint64_t Count) const override {
// Cannot emit NOP with size not multiple of 32 bits.
if (Count % 4 != 0)
return false;
uint64_t NumNops = Count / 4;
for (uint64_t i = 0; i != NumNops; ++i)
- OW->write32(0x01000000);
+ support::endian::write<uint32_t>(OS, 0x01000000, Endian);
return true;
}
@@ -287,7 +286,7 @@ namespace {
// from the fixup value. The Value has been "split up" into the
// appropriate bitfields above.
for (unsigned i = 0; i != 4; ++i) {
- unsigned Idx = IsLittleEndian ? i : 3 - i;
+ unsigned Idx = Endian == support::little ? i : 3 - i;
Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
}
}
@@ -295,7 +294,8 @@ namespace {
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override {
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
- return createSparcELFObjectWriter(OS, Is64Bit, IsLittleEndian, OSABI);
+ return createSparcELFObjectWriter(OS, Is64Bit,
+ Endian == support::little, OSABI);
}
};
Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp Mon May 21 10:57:19 2018
@@ -44,7 +44,7 @@ class SystemZMCAsmBackend : public MCAsm
uint8_t OSABI;
public:
SystemZMCAsmBackend(uint8_t osABI)
- : OSABI(osABI) {}
+ : MCAsmBackend(support::big), OSABI(osABI) {}
// Override MCAsmBackend
unsigned getNumFixupKinds() const override {
@@ -66,7 +66,7 @@ public:
MCInst &Res) const override {
llvm_unreachable("SystemZ does do not have assembler relaxation");
}
- bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+ bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override {
return createSystemZObjectWriter(OS, OSABI);
@@ -115,10 +115,9 @@ void SystemZMCAsmBackend::applyFixup(con
}
}
-bool SystemZMCAsmBackend::writeNopData(uint64_t Count,
- MCObjectWriter *OW) const {
+bool SystemZMCAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
for (uint64_t I = 0; I != Count; ++I)
- OW->write8(7);
+ OS << '\x7';
return true;
}
Modified: llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp Mon May 21 10:57:19 2018
@@ -34,7 +34,7 @@ class WebAssemblyAsmBackendELF final : p
public:
explicit WebAssemblyAsmBackendELF(bool Is64Bit)
- : MCAsmBackend(), Is64Bit(Is64Bit) {}
+ : MCAsmBackend(support::little), Is64Bit(Is64Bit) {}
~WebAssemblyAsmBackendELF() override {}
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
@@ -62,7 +62,7 @@ public:
void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
MCInst &Res) const override {}
- bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+ bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
};
class WebAssemblyAsmBackend final : public MCAsmBackend {
@@ -70,7 +70,7 @@ class WebAssemblyAsmBackend final : publ
public:
explicit WebAssemblyAsmBackend(bool Is64Bit)
- : MCAsmBackend(), Is64Bit(Is64Bit) {}
+ : MCAsmBackend(support::little), Is64Bit(Is64Bit) {}
~WebAssemblyAsmBackend() override {}
unsigned getNumFixupKinds() const override {
@@ -98,13 +98,13 @@ public:
void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
MCInst &Res) const override {}
- bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+ bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
};
-bool WebAssemblyAsmBackendELF::writeNopData(uint64_t Count,
- MCObjectWriter *OW) const {
+bool WebAssemblyAsmBackendELF::writeNopData(raw_ostream &OS,
+ uint64_t Count) const {
for (uint64_t i = 0; i < Count; ++i)
- OW->write8(WebAssembly::Nop);
+ OS << char(WebAssembly::Nop);
return true;
}
@@ -158,13 +158,13 @@ WebAssemblyAsmBackend::getFixupKindInfo(
return Infos[Kind - FirstTargetFixupKind];
}
-bool WebAssemblyAsmBackend::writeNopData(uint64_t Count,
- MCObjectWriter *OW) const {
+bool WebAssemblyAsmBackend::writeNopData(raw_ostream &OS,
+ uint64_t Count) const {
if (Count == 0)
return true;
for (uint64_t i = 0; i < Count; ++i)
- OW->write8(WebAssembly::Nop);
+ OS << char(WebAssembly::Nop);
return true;
}
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=332857&r1=332856&r2=332857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Mon May 21 10:57:19 2018
@@ -71,7 +71,7 @@ class X86AsmBackend : public MCAsmBacken
const MCSubtargetInfo &STI;
public:
X86AsmBackend(const Target &T, const MCSubtargetInfo &STI)
- : MCAsmBackend(), STI(STI) {}
+ : MCAsmBackend(support::little), STI(STI) {}
unsigned getNumFixupKinds() const override {
return X86::NumTargetFixupKinds;
@@ -126,7 +126,7 @@ public:
void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
MCInst &Res) const override;
- bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+ bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
};
} // end anonymous namespace
@@ -315,35 +315,35 @@ void X86AsmBackend::relaxInstruction(con
/// Write a sequence of optimal nops to the output, covering \p Count
/// bytes.
/// \return - true on success, false on failure
-bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
- static const uint8_t Nops[10][10] = {
+bool X86AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+ static const char Nops[10][11] = {
// nop
- {0x90},
+ "\x90",
// xchg %ax,%ax
- {0x66, 0x90},
+ "\x66\x90",
// nopl (%[re]ax)
- {0x0f, 0x1f, 0x00},
+ "\x0f\x1f\x00",
// nopl 0(%[re]ax)
- {0x0f, 0x1f, 0x40, 0x00},
+ "\x0f\x1f\x40\x00",
// nopl 0(%[re]ax,%[re]ax,1)
- {0x0f, 0x1f, 0x44, 0x00, 0x00},
+ "\x0f\x1f\x44\x00\x00",
// nopw 0(%[re]ax,%[re]ax,1)
- {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
+ "\x66\x0f\x1f\x44\x00\x00",
// nopl 0L(%[re]ax)
- {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
+ "\x0f\x1f\x80\x00\x00\x00\x00",
// nopl 0L(%[re]ax,%[re]ax,1)
- {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
+ "\x0f\x1f\x84\x00\x00\x00\x00\x00",
// nopw 0L(%[re]ax,%[re]ax,1)
- {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
+ "\x66\x0f\x1f\x84\x00\x00\x00\x00\x00",
// nopw %cs:0L(%[re]ax,%[re]ax,1)
- {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
+ "\x66\x2e\x0f\x1f\x84\x00\x00\x00\x00\x00",
};
// This CPU doesn't support long nops. If needed add more.
// FIXME: We could generated something better than plain 0x90.
if (!STI.getFeatureBits()[X86::FeatureNOPL]) {
for (uint64_t i = 0; i < Count; ++i)
- OW->write8(0x90);
+ OS << '\x90';
return true;
}
@@ -363,10 +363,9 @@ bool X86AsmBackend::writeNopData(uint64_
const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength);
const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
for (uint8_t i = 0; i < Prefixes; i++)
- OW->write8(0x66);
+ OS << '\x66';
const uint8_t Rest = ThisNopLength - Prefixes;
- for (uint8_t i = 0; i < Rest; i++)
- OW->write8(Nops[Rest - 1][i]);
+ OS.write(Nops[Rest - 1], Rest);
Count -= ThisNopLength;
} while (Count != 0);
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