[PATCH] D47141: [x86] invpcid LLVM intrinsic

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: lib/Target/X86/X86.td:248
                                      "Pad short functions">;
+def FeatureINVPCID : SubtargetFeature<"invpcid", "HasInvPCId", "true",
+                                      "Invalidate Process-Context Identifier">;
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HasINVPCID. It's the name of an instruction so we should keep the caps.


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Comment at: lib/Target/X86/X86InstrInfo.td:907
 def HasWAITPKG   : Predicate<"Subtarget->hasWAITPKG()">;
+def HasINVPCID   : Predicate<"Subtarget->hasInvPCId()">;
 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
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hasINVPCID


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Comment at: lib/Target/X86/X86InstrSystem.td:653
+  def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2),
+            (INVPCID64 (SUBREG_TO_REG (i64 0), GR32:$src1, sub_32bit),
+             addr:$src2)>;
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SUBREG_TO_REG should only be used if you know absolutely the instruction that produced $src1 zeroed the upper bits. You would need to analyze the DAG to prove it. See the "def32" PatLeaf in X86InstrCompiler.td. If it can't be proven, you need a fall back pattern to use a MOV32rr instruction to force zeroes into the upper bits.


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Comment at: test/CodeGen/X86/invpcid-intrinsic.ll:38
+entry:
+  %0 = load i32, i32* %type, align 4
+  tail call void @llvm.x86.invpcid(i32 %0, i8* %descriptor) #1
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Why are you testing with a load for type, but not testing without a load?


Repository:
  rL LLVM

https://reviews.llvm.org/D47141