[llvm] r332844 - [X86][SSE] Add an assert to ensure that rotation amount is converted to a scale
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon May 21 08:17:23 PDT 2018
Author: rksimon
Date: Mon May 21 08:17:23 2018
New Revision: 332844
URL: http://llvm.org/viewvc/llvm-project?rev=332844&view=rev
Log:
[X86][SSE] Add an assert to ensure that rotation amount is converted to a scale
Missed in rL332832 where we added SSE v4i32 rotations for PR37426.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=332844&r1=332843&r2=332844&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon May 21 08:17:23 2018
@@ -23825,6 +23825,7 @@ static SDValue LowerRotate(SDValue Op, c
// to v2i64 results at a time. The upper 32-bits contain the wrapped bits
// that can then be OR'd with the lower 32-bits.
Amt = convertShiftLeftToScale(Amt, DL, Subtarget, DAG);
+ assert(Amt && "Failed to convert ROTL amount to scale");
static const int OddMask[] = {1, -1, 3, -1};
SDValue R13 = DAG.getVectorShuffle(VT, DL, R, R, OddMask);
More information about the llvm-commits
mailing list