[PATCH] D47129: Testcase for PR31593
Katya Romanova via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 21 01:45:18 PDT 2018
kromanova created this revision.
kromanova added a reviewer: craig.topper.
Herald added a subscriber: llvm-commits.
I added a testcase for PR31593. A patch (r291535) that fixed this bug didn't have a testcase.
If you run the testcase with the compiler between r291120 that introduced the problem and r291535 that fixed the problem,
you'll get the following error:
FAIL: LLVM :: CodeGen/X86/pr31593.ll (10654 of 19223)
- TEST 'LLVM :: CodeGen/X86/pr31593.ll' FAILED ********************
Script:
-------
ngh/ToT/build/./bin/llc < ngh/ToT/llvm/test/CodeGen/X86/pr31593.ll -mtriple=x86_64-unknown -mattr=sse4.1 -o /dev/null
---------------------------------------------------------------------------------------------------------------------
Exit Code: 1
Command Output (stderr):
------------------------
LLVM ERROR: Cannot select: t14: v2i64 = zero_extend_vector_inreg t18
t18: v4i32 = bitcast t17
t17: v2i64,ch = load<LD16[%0](dereferenceable)> t0, FrameIndex:i64<1>, undef:i64
t1: i64 = FrameIndex<1>
t3: i64 = undef
In function: _Z3foov
Repository:
rL LLVM
https://reviews.llvm.org/D47129
Files:
test/CodeGen/X86/pr31593.ll
Index: test/CodeGen/X86/pr31593.ll
===================================================================
--- test/CodeGen/X86/pr31593.ll
+++ test/CodeGen/X86/pr31593.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=sse4.1 -o /dev/null
+
+; Testcase for PR31593.
+; Revision r291120 introduced a regression and this test started failing
+; because of a 'fatal error in the backend':
+; Cannot select: t14: v2i64 = zero_extend_vector_inreg t18
+; t18: v4i32 = bitcast t17
+; t17: v2i64,ch = load<LD16[%0](dereferenceable)> t0, FrameIndex:i64<1>, undef:i64
+; t1: i64 = FrameIndex<1>
+; t3: i64 = undef
+; In function: _Z3foov
+; This regression was fixed in r291535.
+
+%struct.S = type { <2 x i64> }
+
+define i32 @_ZNK1S1aEv(%struct.S* nocapture readonly %this) local_unnamed_addr #0 align 2 {
+entry:
+ %0 = bitcast %struct.S* %this to <4 x i32>*
+ %1 = load <4 x i32>, <4 x i32>* %0, align 16
+ %vecext = extractelement <4 x i32> %1, i32 0
+ ret i32 %vecext
+}
+declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32)
+define void @_Z3foov() local_unnamed_addr #2 {
+entry:
+ %zero = alloca %struct.S, align 16
+ %e = alloca %struct.S, align 16
+ %s = alloca %struct.S, align 16
+ %0 = bitcast %struct.S* %zero to i8*
+ %1 = bitcast %struct.S* %e to i8*
+ %2 = bitcast %struct.S* %e to <4 x i32>*
+ %3 = load <4 x i32>, <4 x i32>* %2, align 16
+ %vecext.i = extractelement <4 x i32> %3, i32 0
+ %4 = bitcast %struct.S* %s to i8*
+ %5 = bitcast %struct.S* %s to <4 x i32>*
+ %6 = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 %vecext.i)
+ store <4 x i32> %6, <4 x i32>* %5, align 16
+ ret void
+}
+attributes #2 = { "target-features"="+sse4.1" }
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