[llvm] r332748 - [Hexagon] Generate post-increment for floating point types
Brendon Cahoon via llvm-commits
llvm-commits at lists.llvm.org
Fri May 18 11:14:44 PDT 2018
Author: bcahoon
Date: Fri May 18 11:14:44 2018
New Revision: 332748
URL: http://llvm.org/viewvc/llvm-project?rev=332748&view=rev
Log:
[Hexagon] Generate post-increment for floating point types
The code that generates post-increments for Hexagon considered
integer values only. This patch adds support to generate them for
floating point values, f32 and f64.
Differential Revision: https://reviews.llvm.org/D47036
Added:
llvm/trunk/test/CodeGen/Hexagon/postinc-float.ll
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/test/CodeGen/Hexagon/swp-memrefs-epilog.ll
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=332748&r1=332747&r2=332748&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp Fri May 18 11:14:44 2018
@@ -93,11 +93,13 @@ void HexagonDAGToDAGISel::SelectIndexedL
Opcode = IsValidInc ? Hexagon::L2_loadrh_pi : Hexagon::L2_loadrh_io;
break;
case MVT::i32:
+ case MVT::f32:
case MVT::v2i16:
case MVT::v4i8:
Opcode = IsValidInc ? Hexagon::L2_loadri_pi : Hexagon::L2_loadri_io;
break;
case MVT::i64:
+ case MVT::f64:
case MVT::v2i32:
case MVT::v4i16:
case MVT::v8i8:
@@ -483,11 +485,13 @@ void HexagonDAGToDAGISel::SelectIndexedS
Opcode = IsValidInc ? Hexagon::S2_storerh_pi : Hexagon::S2_storerh_io;
break;
case MVT::i32:
+ case MVT::f32:
case MVT::v2i16:
case MVT::v4i8:
Opcode = IsValidInc ? Hexagon::S2_storeri_pi : Hexagon::S2_storeri_io;
break;
case MVT::i64:
+ case MVT::f64:
case MVT::v2i32:
case MVT::v4i16:
case MVT::v8i8:
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=332748&r1=332747&r2=332748&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Fri May 18 11:14:44 2018
@@ -550,8 +550,9 @@ bool HexagonTargetLowering::getPostIndex
if (!VT.isSimple())
return false;
bool IsLegalType = VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
- VT == MVT::i64 || VT == MVT::v2i16 || VT == MVT::v2i32 ||
- VT == MVT::v4i8 || VT == MVT::v4i16 || VT == MVT::v8i8 ||
+ VT == MVT::i64 || VT == MVT::f32 || VT == MVT::f64 ||
+ VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 ||
+ VT == MVT::v4i16 || VT == MVT::v8i8 ||
Subtarget.isHVXVectorType(VT.getSimpleVT());
if (!IsLegalType)
return false;
@@ -1579,8 +1580,8 @@ HexagonTargetLowering::HexagonTargetLowe
// Handling of indexed loads/stores: default is "expand".
//
- for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64, MVT::v2i16,
- MVT::v2i32, MVT::v4i8, MVT::v4i16, MVT::v8i8}) {
+ for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64, MVT::f32, MVT::f64,
+ MVT::v2i16, MVT::v2i32, MVT::v4i8, MVT::v4i16, MVT::v8i8}) {
setIndexedLoadAction(ISD::POST_INC, VT, Legal);
setIndexedStoreAction(ISD::POST_INC, VT, Legal);
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=332748&r1=332747&r2=332748&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Fri May 18 11:14:44 2018
@@ -2585,6 +2585,8 @@ bool HexagonInstrInfo::isValidAutoIncImm
case MVT::i16:
case MVT::i32:
case MVT::i64:
+ case MVT::f32:
+ case MVT::f64:
case MVT::v2i16:
case MVT::v2i32:
case MVT::v4i8:
Added: llvm/trunk/test/CodeGen/Hexagon/postinc-float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/postinc-float.ll?rev=332748&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/postinc-float.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/postinc-float.ll Fri May 18 11:14:44 2018
@@ -0,0 +1,86 @@
+; RUN: llc -mtriple=hexagon-unknown-elf < %s | FileCheck %s
+
+; CHECK-LABEL: ldf
+; CHECK: memw(r{{[0-9]+}}++#4)
+; CHECK: memw(r{{[0-9]+}}++#4)
+define float @ldf(float* nocapture readonly %x, float* nocapture readonly %y) local_unnamed_addr #0 {
+entry:
+ br label %for.body
+
+for.body:
+ %arrayidx.phi = phi float* [ %x, %entry ], [ %arrayidx.inc, %for.body ]
+ %arrayidx1.phi = phi float* [ %y, %entry ], [ %arrayidx1.inc, %for.body ]
+ %i.09 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+ %acc.08 = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]
+ %0 = load float, float* %arrayidx.phi, align 4
+ %1 = load float, float* %arrayidx1.phi, align 4
+ %mul = fmul contract float %0, %1
+ %add = fadd contract float %acc.08, %mul
+ %inc = add nuw nsw i32 %i.09, 1
+ %exitcond = icmp eq i32 %inc, 1024
+ %arrayidx.inc = getelementptr float, float* %arrayidx.phi, i32 1
+ %arrayidx1.inc = getelementptr float, float* %arrayidx1.phi, i32 1
+ br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+ ret float %add
+}
+
+; CHECK-LABEL: ldd
+; CHECK: memd(r{{[0-9]+}}++#8)
+; CHECK: memd(r{{[0-9]+}}++#8)
+define double @ldd(double* nocapture readonly %x, double* nocapture readonly %y) local_unnamed_addr #0 {
+entry:
+ br label %for.body
+
+for.body:
+ %arrayidx.phi = phi double* [ %x, %entry ], [ %arrayidx.inc, %for.body ]
+ %arrayidx1.phi = phi double* [ %y, %entry ], [ %arrayidx1.inc, %for.body ]
+ %i.09 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+ %acc.08 = phi double [ 0.000000e+00, %entry ], [ %add, %for.body ]
+ %0 = load double, double* %arrayidx.phi, align 8
+ %1 = load double, double* %arrayidx1.phi, align 8
+ %mul = fmul contract double %0, %1
+ %add = fadd contract double %acc.08, %mul
+ %inc = add nuw nsw i32 %i.09, 1
+ %exitcond = icmp eq i32 %inc, 1024
+ %arrayidx.inc = getelementptr double, double* %arrayidx.phi, i32 1
+ %arrayidx1.inc = getelementptr double, double* %arrayidx1.phi, i32 1
+ br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+ ret double %add
+}
+
+; CHECK-LABEL: stf
+; CHECK: memw(r{{[0-9]+}}++#4)
+define double* @stf(float* returned %p) local_unnamed_addr #0 {
+entry:
+ br label %for.body
+
+for.body:
+ %arrayidx.phi = phi float* [ %arrayidx.inc, %for.body ], [ %p, %entry ]
+ %call = tail call float @foof() #2
+ store float %call, float* %arrayidx.phi, align 8
+ %arrayidx.inc = getelementptr float, float* %arrayidx.phi, i32 1
+ br label %for.body
+}
+
+declare float @foof() local_unnamed_addr #1
+
+; CHECK-LABEL: std
+; CHECK: memd(r{{[0-9]+}}++#8)
+define double* @std(double* returned %p) local_unnamed_addr #0 {
+entry:
+ br label %for.body
+
+for.body:
+ %arrayidx.phi = phi double* [ %arrayidx.inc, %for.body ], [ %p, %entry ]
+ %call = tail call double @food() #2
+ store double %call, double* %arrayidx.phi, align 8
+ %arrayidx.inc = getelementptr double, double* %arrayidx.phi, i32 1
+ br label %for.body
+}
+
+declare double @food() local_unnamed_addr #1
+
Modified: llvm/trunk/test/CodeGen/Hexagon/swp-memrefs-epilog.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-memrefs-epilog.ll?rev=332748&r1=332747&r2=332748&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/swp-memrefs-epilog.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/swp-memrefs-epilog.ll Fri May 18 11:14:44 2018
@@ -10,8 +10,7 @@
; to r29+32. If the memoperands are updated incorrectly, these are swapped.
; CHECK: [[REG0:r([0-9]+)]] = add(r29,#24)
-; CHECK: [[REG1:r([0-9]+)]] = add([[REG0]],#4)
-; CHECK: memw([[REG1]]+#{{[0-9]}}) = r{{[0-9]+}}
+; CHECK: memw([[REG0]]++#4) = r{{[0-9]+}}
; CHECK: r{{[0-9]+}} = memw(r29+#{{[0-9]+}})
%s.0 = type { %s.1 }
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