[PATCH] D46754: [AMDGPU] Add intrinsics for 16 bit interpolation

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In https://reviews.llvm.org/D46754#1104799, @arsenm wrote:

> In https://reviews.llvm.org/D46754#1104736, @timcorringham wrote:
>
> > Corrected the ordering of operands to interp_p2_f16, added lowered 
> >  intrinsics to list of those that cware a source of divergence, and
> >  amended LIT test.
> >
> > I have not overloaded the intrinsics as I don't believe it is possible
> >  in this case as they have an additional operand, and apart from that 
> >  additional operand the interp_p1_f16 has the same types as the 32 bit
> >  version, so there are no type differences to provide disambiguation.
>
>
> Is the extra parameter you're referring the high parameter to change where the register is read from the high or low bits? That shouldn't be exposed in the intrinsic at all. Eliminating the high bit extraction is a codegen optimization pattern


Or is this bit controlling the weird load from memory? The manual isn't particularly clear to me. I see mention of LDs loads, but also op_sel control of destination bits


Repository:
  rL LLVM

https://reviews.llvm.org/D46754