[llvm] r332718 - [X86][SSE] Ensure vector partial load/stores use the WriteVecLoad/WriteVecStore scheduler classes
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri May 18 07:08:02 PDT 2018
Author: rksimon
Date: Fri May 18 07:08:01 2018
New Revision: 332718
URL: http://llvm.org/viewvc/llvm-project?rev=332718&view=rev
Log:
[X86][SSE] Ensure vector partial load/stores use the WriteVecLoad/WriteVecStore scheduler classes
Retag some instructions that were missed when we split off vector load/store/moves - MOVQ/MOVD etc.
Fixes BtVer2/SLM which have different behaviours for GPR stores.
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrMMX.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s
llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-mmx.s
llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-sse2.s
llvm/trunk/test/tools/llvm-mca/X86/SLM/resources-mmx.s
llvm/trunk/test/tools/llvm-mca/X86/SLM/resources-sse2.s
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=332718&r1=332717&r2=332718&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Fri May 18 07:08:01 2018
@@ -3622,7 +3622,7 @@ def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSr
"vmovd\t{$src, $dst|$dst, $src}",
[(set VR128X:$dst,
(v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
- EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteLoad]>;
+ EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecLoad]>;
def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
"vmovq\t{$src, $dst|$dst, $src}",
[(set VR128X:$dst,
@@ -3632,7 +3632,7 @@ let isCodeGenOnly = 1, ForceDisassemble
def VMOV64toPQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
(ins i64mem:$src),
"vmovq\t{$src, $dst|$dst, $src}", []>,
- EVEX, VEX_W, EVEX_CD8<64, CD8VT1>, Sched<[WriteLoad]>;
+ EVEX, VEX_W, EVEX_CD8<64, CD8VT1>, Sched<[WriteVecLoad]>;
let isCodeGenOnly = 1 in {
def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64X:$dst), (ins GR64:$src),
"vmovq\t{$src, $dst|$dst, $src}",
@@ -3641,7 +3641,7 @@ def VMOV64toSDZrr : AVX512BI<0x6E, MRMSr
def VMOV64toSDZrm : AVX512XSI<0x7E, MRMSrcMem, (outs FR64X:$dst), (ins i64mem:$src),
"vmovq\t{$src, $dst|$dst, $src}",
[(set FR64X:$dst, (bitconvert (loadi64 addr:$src)))]>,
- EVEX, VEX_W, EVEX_CD8<8, CD8VT8>, Sched<[WriteLoad]>;
+ EVEX, VEX_W, EVEX_CD8<8, CD8VT8>, Sched<[WriteVecLoad]>;
def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64X:$src),
"vmovq\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (bitconvert FR64X:$src))]>,
@@ -3649,7 +3649,7 @@ def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDe
def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64X:$src),
"vmovq\t{$src, $dst|$dst, $src}",
[(store (i64 (bitconvert FR64X:$src)), addr:$dst)]>,
- EVEX, VEX_W, Sched<[WriteStore]>,
+ EVEX, VEX_W, Sched<[WriteVecStore]>,
EVEX_CD8<64, CD8VT1>;
}
} // ExeDomain = SSEPackedInt
@@ -3665,7 +3665,7 @@ def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSr
def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
"vmovd\t{$src, $dst|$dst, $src}",
[(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))]>,
- EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteLoad]>;
+ EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecLoad]>;
} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1
// Move doubleword from xmm register to r/m32
@@ -3681,7 +3681,7 @@ def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMD
"vmovd\t{$src, $dst|$dst, $src}",
[(store (i32 (extractelt (v4i32 VR128X:$src),
(iPTR 0))), addr:$dst)]>,
- EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteStore]>;
+ EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecStore]>;
} // ExeDomain = SSEPackedInt
// Move quadword from xmm1 register to r/m64
@@ -3697,7 +3697,7 @@ def VMOVPQIto64Zrr : I<0x7E, MRMDestReg,
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
def VMOVPQIto64Zmr : I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128X:$src),
"vmovq\t{$src, $dst|$dst, $src}", []>, PD,
- EVEX, VEX_W, Sched<[WriteStore]>,
+ EVEX, VEX_W, Sched<[WriteVecStore]>,
Requires<[HasAVX512, In64BitMode]>;
def VMOVPQI2QIZmr : I<0xD6, MRMDestMem, (outs),
@@ -3706,7 +3706,7 @@ def VMOVPQI2QIZmr : I<0xD6, MRMDestMem,
[(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
addr:$dst)]>,
EVEX, PD, VEX_W, EVEX_CD8<64, CD8VT1>,
- Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
+ Sched<[WriteVecStore]>, Requires<[HasAVX512, In64BitMode]>;
let hasSideEffects = 0 in
def VMOVPQI2QIZrr : AVX512BI<0xD6, MRMDestReg, (outs VR128X:$dst),
@@ -3727,7 +3727,7 @@ def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDe
(ins i32mem:$dst, FR32X:$src),
"vmovd\t{$src, $dst|$dst, $src}",
[(store (i32 (bitconvert FR32X:$src)), addr:$dst)]>,
- EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteStore]>;
+ EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecStore]>;
} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1
// Move Quadword Int to Packed Quadword Int
@@ -3738,7 +3738,7 @@ def VMOVQI2PQIZrm : AVX512XSI<0x7E, MRMS
"vmovq\t{$src, $dst|$dst, $src}",
[(set VR128X:$dst,
(v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
- EVEX, VEX_W, EVEX_CD8<8, CD8VT8>, Sched<[WriteLoad]>;
+ EVEX, VEX_W, EVEX_CD8<8, CD8VT8>, Sched<[WriteVecLoad]>;
} // ExeDomain = SSEPackedInt
// Allow "vmovd" but print "vmovq".
Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=332718&r1=332717&r2=332718&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Fri May 18 07:08:01 2018
@@ -170,7 +170,7 @@ def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem,
"movd\t{$src, $dst|$dst, $src}",
[(set VR64:$dst,
(x86mmx (scalar_to_vector (loadi32 addr:$src))))]>,
- Sched<[WriteLoad]>;
+ Sched<[WriteVecLoad]>;
let Predicates = [HasMMX] in {
let AddedComplexity = 15 in
@@ -187,7 +187,7 @@ let Predicates = [HasMMX] in {
let mayStore = 1 in
def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
"movd\t{$src, $dst|$dst, $src}", []>,
- Sched<[WriteStore]>;
+ Sched<[WriteVecStore]>;
def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src),
"movd\t{$src, $dst|$dst, $src}",
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=332718&r1=332717&r2=332718&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri May 18 07:08:01 2018
@@ -3970,7 +3970,7 @@ def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem,
"movd\t{$src, $dst|$dst, $src}",
[(set VR128:$dst,
(v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
- VEX, Sched<[WriteLoad]>;
+ VEX, Sched<[WriteVecLoad]>;
def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
"movq\t{$src, $dst|$dst, $src}",
[(set VR128:$dst,
@@ -3979,7 +3979,7 @@ def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcRe
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
def VMOV64toPQIrm : VRS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
"movq\t{$src, $dst|$dst, $src}", []>,
- VEX, Sched<[WriteLoad]>;
+ VEX, Sched<[WriteVecLoad]>;
let isCodeGenOnly = 1 in
def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
"movq\t{$src, $dst|$dst, $src}",
@@ -3995,7 +3995,7 @@ def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (
"movd\t{$src, $dst|$dst, $src}",
[(set VR128:$dst,
(v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
- Sched<[WriteLoad]>;
+ Sched<[WriteVecLoad]>;
def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
"movq\t{$src, $dst|$dst, $src}",
[(set VR128:$dst,
@@ -4004,7 +4004,7 @@ def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg,
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
def MOV64toPQIrm : RS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
"movq\t{$src, $dst|$dst, $src}", []>,
- Sched<[WriteLoad]>;
+ Sched<[WriteVecLoad]>;
let isCodeGenOnly = 1 in
def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
"movq\t{$src, $dst|$dst, $src}",
@@ -4024,7 +4024,7 @@ let ExeDomain = SSEPackedInt, isCodeGenO
def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
"movd\t{$src, $dst|$dst, $src}",
[(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
- VEX, Sched<[WriteLoad]>;
+ VEX, Sched<[WriteVecLoad]>;
def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
"movd\t{$src, $dst|$dst, $src}",
[(set FR32:$dst, (bitconvert GR32:$src))]>,
@@ -4033,7 +4033,7 @@ let ExeDomain = SSEPackedInt, isCodeGenO
def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
"movd\t{$src, $dst|$dst, $src}",
[(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
- Sched<[WriteLoad]>;
+ Sched<[WriteVecLoad]>;
} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1
//===---------------------------------------------------------------------===//
@@ -4050,7 +4050,7 @@ def VMOVPDI2DImr : VS2I<0x7E, MRMDestMe
"movd\t{$src, $dst|$dst, $src}",
[(store (i32 (extractelt (v4i32 VR128:$src),
(iPTR 0))), addr:$dst)]>,
- VEX, Sched<[WriteStore]>;
+ VEX, Sched<[WriteVecStore]>;
def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
"movd\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (extractelt (v4i32 VR128:$src),
@@ -4060,7 +4060,7 @@ def MOVPDI2DImr : S2I<0x7E, MRMDestMem,
"movd\t{$src, $dst|$dst, $src}",
[(store (i32 (extractelt (v4i32 VR128:$src),
(iPTR 0))), addr:$dst)]>,
- Sched<[WriteStore]>;
+ Sched<[WriteVecStore]>;
} // ExeDomain = SSEPackedInt
//===---------------------------------------------------------------------===//
@@ -4084,11 +4084,11 @@ let isCodeGenOnly = 1, ForceDisassemble
def VMOVPQIto64mr : VRS2I<0x7E, MRMDestMem, (outs),
(ins i64mem:$dst, VR128:$src),
"movq\t{$src, $dst|$dst, $src}", []>,
- VEX, Sched<[WriteStore]>;
+ VEX, Sched<[WriteVecStore]>;
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
def MOVPQIto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
"movq\t{$src, $dst|$dst, $src}", []>,
- Sched<[WriteStore]>;
+ Sched<[WriteVecStore]>;
} // ExeDomain = SSEPackedInt
//===---------------------------------------------------------------------===//
@@ -4099,7 +4099,7 @@ let ExeDomain = SSEPackedInt, isCodeGenO
def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
"movq\t{$src, $dst|$dst, $src}",
[(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
- VEX, Sched<[WriteLoad]>;
+ VEX, Sched<[WriteVecLoad]>;
def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
"movq\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (bitconvert FR64:$src))]>,
@@ -4107,12 +4107,12 @@ let ExeDomain = SSEPackedInt, isCodeGenO
def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
"movq\t{$src, $dst|$dst, $src}",
[(store (i64 (bitconvert FR64:$src)), addr:$dst)]>,
- VEX, Sched<[WriteStore]>;
+ VEX, Sched<[WriteVecStore]>;
def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
"movq\t{$src, $dst|$dst, $src}",
[(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
- Sched<[WriteLoad]>;
+ Sched<[WriteVecLoad]>;
def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
"movq\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (bitconvert FR64:$src))]>,
@@ -4120,7 +4120,7 @@ let ExeDomain = SSEPackedInt, isCodeGenO
def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
"movq\t{$src, $dst|$dst, $src}",
[(store (i64 (bitconvert FR64:$src)), addr:$dst)]>,
- Sched<[WriteStore]>;
+ Sched<[WriteVecStore]>;
} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1
//===---------------------------------------------------------------------===//
@@ -4134,7 +4134,7 @@ let ExeDomain = SSEPackedInt, isCodeGenO
def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
"movd\t{$src, $dst|$dst, $src}",
[(store (i32 (bitconvert FR32:$src)), addr:$dst)]>,
- VEX, Sched<[WriteStore]>;
+ VEX, Sched<[WriteVecStore]>;
def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
"movd\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (bitconvert FR32:$src))]>,
@@ -4142,7 +4142,7 @@ let ExeDomain = SSEPackedInt, isCodeGenO
def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
"movd\t{$src, $dst|$dst, $src}",
[(store (i32 (bitconvert FR32:$src)), addr:$dst)]>,
- Sched<[WriteStore]>;
+ Sched<[WriteVecStore]>;
} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1
let Predicates = [UseAVX] in {
@@ -4225,7 +4225,7 @@ def : InstAlias<"vmovd\t{$src, $dst|$dst
// Move Quadword Int to Packed Quadword Int
//
-let ExeDomain = SSEPackedInt, SchedRW = [WriteLoad] in {
+let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLoad] in {
def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
"vmovq\t{$src, $dst|$dst, $src}",
[(set VR128:$dst,
@@ -4241,7 +4241,7 @@ def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ou
//===---------------------------------------------------------------------===//
// Move Packed Quadword Int to Quadword Int
//
-let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
+let ExeDomain = SSEPackedInt, SchedRW = [WriteVecStore] in {
def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
"movq\t{$src, $dst|$dst, $src}",
[(store (i64 (extractelt (v2i64 VR128:$src),
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=332718&r1=332717&r2=332718&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Fri May 18 07:08:01 2018
@@ -600,13 +600,7 @@ def BWWriteResGroup10 : SchedWriteRes<[B
let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm",
- "MMX_MOVD64mr",
- "ST_FP(32|64|80)m",
- "(V?)MOV(H|L)(PD|PS)mr",
- "(V?)MOVPDI2DImr",
- "(V?)MOVPQI2QImr",
- "(V?)MOVPQIto64mr",
- "(V?)MOV(SD|SS)mr")>;
+ "ST_FP(32|64|80)m")>;
def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
let Latency = 2;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=332718&r1=332717&r2=332718&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Fri May 18 07:08:01 2018
@@ -786,13 +786,7 @@ def HWWriteResGroup1 : SchedWriteRes<[HW
let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup1], (instregex "FBSTPm",
- "MMX_MOVD64mr",
"ST_FP(32|64|80)m",
- "(V?)MOV(H|L)(PD|PS)mr",
- "(V?)MOVPDI2DImr",
- "(V?)MOVPQI2QImr",
- "(V?)MOVPQIto64mr",
- "(V?)MOV(SD|SS)mr",
"VMPTRSTm")>;
def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> {
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=332718&r1=332717&r2=332718&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Fri May 18 07:08:01 2018
@@ -602,13 +602,7 @@ def SKLWriteResGroup11 : SchedWriteRes<[
let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup11], (instregex "FBSTPm",
- "MMX_MOVD64mr",
"ST_FP(32|64|80)m",
- "(V?)MOV(H|L)(PD|PS)mr",
- "(V?)MOVPDI2DImr",
- "(V?)MOVPQI2QImr",
- "(V?)MOVPQIto64mr",
- "(V?)MOV(SD|SS)mr",
"VMPTRSTm")>;
def SKLWriteResGroup12 : SchedWriteRes<[SKLPort0]> {
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=332718&r1=332717&r2=332718&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Fri May 18 07:08:01 2018
@@ -627,17 +627,7 @@ def SKXWriteResGroup11 : SchedWriteRes<[
}
def: InstRW<[SKXWriteResGroup11], (instregex "FBSTPm",
"KMOV(B|D|Q|W)mk",
- "MMX_MOVD64mr",
"ST_FP(32|64|80)m",
- "VMOV(H|L)(PD|PS)Z128mr(b?)",
- "(V?)MOV(H|L)(PD|PS)mr",
- "VMOVPDI2DIZmr(b?)",
- "(V?)MOVPDI2DImr",
- "VMOVPQI(2QI|to64)Zmr(b?)",
- "(V?)MOVPQI2QImr",
- "(V?)MOVPQIto64mr",
- "VMOV(SD|SS)Zmr(b?)",
- "(V?)MOV(SD|SS)mr",
"VMPTRSTm")>;
def SKXWriteResGroup12 : SchedWriteRes<[SKXPort0]> {
Modified: llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s?rev=332718&r1=332717&r2=332718&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s (original)
+++ llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s Fri May 18 07:08:01 2018
@@ -1720,7 +1720,7 @@ vzeroupper
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
-# CHECK-NEXT: 48.00 2.00 - 350.50 910.50 398.00 418.00 382.00 - 43.00 130.00 118.50 118.50 38.00
+# CHECK-NEXT: 48.00 2.00 - 350.50 910.50 399.00 421.00 382.00 - 43.00 132.00 119.50 119.50 38.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
@@ -1959,9 +1959,9 @@ vzeroupper
# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - vmovaps %ymm0, (%rax)
# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 1.00 - - - - - - vmovaps (%rax), %ymm2
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - vmovd %eax, %xmm2
-# CHECK-NEXT: - - - - - - - 1.00 - - - - - - vmovd (%rax), %xmm2
+# CHECK-NEXT: - - - - - 0.50 0.50 1.00 - - - 0.50 0.50 - vmovd (%rax), %xmm2
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - vmovd %xmm0, %ecx
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - - vmovd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - vmovd %xmm0, (%rax)
# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - vmovddup %xmm0, %xmm2
# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 1.00 - - - - - - vmovddup (%rax), %xmm2
# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - vmovddup %ymm0, %ymm2
@@ -2002,9 +2002,9 @@ vzeroupper
# CHECK-NEXT: - - - - - - 2.00 - - 2.00 2.00 - - - vmovntps %ymm0, (%rax)
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - vmovq %xmm0, %xmm2
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - vmovq %rax, %xmm2
-# CHECK-NEXT: - - - - - - - 1.00 - - - - - - vmovq (%rax), %xmm2
+# CHECK-NEXT: - - - - - 0.50 0.50 1.00 - - - 0.50 0.50 - vmovq (%rax), %xmm2
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - vmovq %xmm0, %rcx
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - - vmovq %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - vmovq %xmm0, (%rax)
# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - vmovsd %xmm0, %xmm1, %xmm2
# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - vmovsd %xmm0, (%rax)
# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 1.00 - - - - - - vmovsd (%rax), %xmm2
Modified: llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-mmx.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-mmx.s?rev=332718&r1=332717&r2=332718&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-mmx.s (original)
+++ llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-mmx.s Fri May 18 07:08:01 2018
@@ -288,15 +288,15 @@ pxor (%rax), %mm2
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
-# CHECK-NEXT: 2.00 2.00 - 0.50 0.50 52.00 47.00 46.00 - 2.00 1.00 45.50 45.50 6.00
+# CHECK-NEXT: 2.00 2.00 - 0.50 0.50 52.50 48.50 46.00 - 2.00 2.00 46.00 46.00 6.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - emms
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movd %eax, %mm2
-# CHECK-NEXT: - - - - - - - 1.00 - - - - - - movd (%rax), %mm2
+# CHECK-NEXT: - - - - - 0.50 0.50 1.00 - - - 0.50 0.50 - movd (%rax), %mm2
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movd %mm0, %ecx
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - - movd %mm0, (%rax)
+# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - movd %mm0, (%rax)
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movq %rax, %mm2
# CHECK-NEXT: - - - - - 0.50 0.50 1.00 - - - 0.50 0.50 - movq (%rax), %mm2
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movq %mm0, %rcx
Modified: llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-sse2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-sse2.s?rev=332718&r1=332717&r2=332718&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-sse2.s (original)
+++ llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-sse2.s Fri May 18 07:08:01 2018
@@ -685,7 +685,7 @@ xorpd (%rax), %xmm2
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
-# CHECK-NEXT: 17.00 2.00 - 46.00 203.00 115.50 136.50 117.00 - 15.00 52.00 65.50 65.50 12.00
+# CHECK-NEXT: 17.00 2.00 - 46.00 203.00 116.50 139.50 117.00 - 15.00 54.00 66.50 66.50 12.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
@@ -760,9 +760,9 @@ xorpd (%rax), %xmm2
# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - movapd %xmm0, (%rax)
# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 1.00 - - - - - - movapd (%rax), %xmm2
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movd %eax, %xmm2
-# CHECK-NEXT: - - - - - - - 1.00 - - - - - - movd (%rax), %xmm2
+# CHECK-NEXT: - - - - - 0.50 0.50 1.00 - - - 0.50 0.50 - movd (%rax), %xmm2
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movd %xmm0, %ecx
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - - movd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - movd %xmm0, (%rax)
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - movdqa %xmm0, %xmm2
# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - movdqa %xmm0, (%rax)
# CHECK-NEXT: - - - - - 0.50 0.50 1.00 - - - 0.50 0.50 - movdqa (%rax), %xmm2
@@ -781,9 +781,9 @@ xorpd (%rax), %xmm2
# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - movntpd %xmm0, (%rax)
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - movq %xmm0, %xmm2
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movq %rax, %xmm2
-# CHECK-NEXT: - - - - - - - 1.00 - - - - - - movq (%rax), %xmm2
+# CHECK-NEXT: - - - - - 0.50 0.50 1.00 - - - 0.50 0.50 - movq (%rax), %xmm2
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movq %xmm0, %rcx
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - - movq %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - movq %xmm0, (%rax)
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - movq2dq %mm0, %xmm2
# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - movsd %xmm0, %xmm2
# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - movsd %xmm0, (%rax)
Modified: llvm/trunk/test/tools/llvm-mca/X86/SLM/resources-mmx.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/SLM/resources-mmx.s?rev=332718&r1=332717&r2=332718&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/SLM/resources-mmx.s (original)
+++ llvm/trunk/test/tools/llvm-mca/X86/SLM/resources-mmx.s Fri May 18 07:08:01 2018
@@ -282,7 +282,7 @@ pxor (%rax), %mm2
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: - - - 77.00 29.00 2.50 2.50 48.00
+# CHECK-NEXT: - - - 77.00 29.00 2.00 2.00 48.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
@@ -290,7 +290,7 @@ pxor (%rax), %mm2
# CHECK-NEXT: - - - - - 0.50 0.50 - movd %eax, %mm2
# CHECK-NEXT: - - - - - - - 1.00 movd (%rax), %mm2
# CHECK-NEXT: - - - - - 0.50 0.50 - movd %mm0, %ecx
-# CHECK-NEXT: - - - - - 0.50 0.50 1.00 movd %mm0, (%rax)
+# CHECK-NEXT: - - - - - - - 1.00 movd %mm0, (%rax)
# CHECK-NEXT: - - - - - 0.50 0.50 - movq %rax, %mm2
# CHECK-NEXT: - - - - - - - 1.00 movq (%rax), %mm2
# CHECK-NEXT: - - - - - 0.50 0.50 - movq %mm0, %rcx
Modified: llvm/trunk/test/tools/llvm-mca/X86/SLM/resources-sse2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/SLM/resources-sse2.s?rev=332718&r1=332717&r2=332718&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/SLM/resources-sse2.s (original)
+++ llvm/trunk/test/tools/llvm-mca/X86/SLM/resources-sse2.s Fri May 18 07:08:01 2018
@@ -679,7 +679,7 @@ xorpd (%rax), %xmm2
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: - 412.00 8.00 150.50 86.50 4.00 4.00 132.00
+# CHECK-NEXT: - 412.00 8.00 150.50 86.50 3.00 3.00 132.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
@@ -756,7 +756,7 @@ xorpd (%rax), %xmm2
# CHECK-NEXT: - - - - - 0.50 0.50 - movd %eax, %xmm2
# CHECK-NEXT: - - - - - - - 1.00 movd (%rax), %xmm2
# CHECK-NEXT: - - - - - 0.50 0.50 - movd %xmm0, %ecx
-# CHECK-NEXT: - - - - - 0.50 0.50 1.00 movd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - 1.00 movd %xmm0, (%rax)
# CHECK-NEXT: - - - 0.50 0.50 - - - movdqa %xmm0, %xmm2
# CHECK-NEXT: - - - - - - - 1.00 movdqa %xmm0, (%rax)
# CHECK-NEXT: - - - - - - - 1.00 movdqa (%rax), %xmm2
@@ -777,7 +777,7 @@ xorpd (%rax), %xmm2
# CHECK-NEXT: - - - - - 0.50 0.50 - movq %rax, %xmm2
# CHECK-NEXT: - - - - - - - 1.00 movq (%rax), %xmm2
# CHECK-NEXT: - - - - - 0.50 0.50 - movq %xmm0, %rcx
-# CHECK-NEXT: - - - - - 0.50 0.50 1.00 movq %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - 1.00 movq %xmm0, (%rax)
# CHECK-NEXT: - - - 0.50 0.50 - - - movq2dq %mm0, %xmm2
# CHECK-NEXT: - - - 1.00 - - - - movsd %xmm0, %xmm2
# CHECK-NEXT: - - - - - - - 1.00 movsd %xmm0, (%rax)
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