Author: courbet
Date: Fri May 18 06:10:41 2018
New Revision: 332713
URL: http://llvm.org/viewvc/llvm-project?rev=332713&view=rev
Log:
[ExynosM3] Fix scheduling info.
Differential Revision: https://reviews.llvm.org/D46356
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td?rev=332713&r1=332712&r2=332713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td Fri May 18 06:10:41 2018
@@ -301,22 +301,22 @@ def M3WriteNEONH : SchedWriteRes<[M3Un
def M3WriteNEONI : SchedWriteRes<[M3UnitNSHF,
M3UnitS]> { let Latency = 5;
let NumMicroOps = 2; }
-def M3WriteNEONV : SchedWriteRes<[M3UnitFDIV,
- M3UnitFDIV]> { let Latency = 7;
- let NumMicroOps = 1;
- let ResourceCycles = [8]; }
-def M3WriteNEONW : SchedWriteRes<[M3UnitFDIV,
- M3UnitFDIV]> { let Latency = 12;
- let NumMicroOps = 1;
- let ResourceCycles = [13]; }
+def M3WriteNEONV : SchedWriteRes<[M3UnitFDIV0,
+ M3UnitFDIV1]> { let Latency = 7;
+ let NumMicroOps = 2;
+ let ResourceCycles = [8, 8]; }
+def M3WriteNEONW : SchedWriteRes<[M3UnitFDIV0,
+ M3UnitFDIV1]> { let Latency = 12;
+ let NumMicroOps = 2;
+ let ResourceCycles = [13, 13]; }
def M3WriteNEONX : SchedWriteRes<[M3UnitFSQR,
M3UnitFSQR]> { let Latency = 18;
- let NumMicroOps = 1;
- let ResourceCycles = [19]; }
+ let NumMicroOps = 2;
+ let ResourceCycles = [19, 19]; }
def M3WriteNEONY : SchedWriteRes<[M3UnitFSQR,
M3UnitFSQR]> { let Latency = 25;
- let NumMicroOps = 1;
- let ResourceCycles = [26]; }
+ let NumMicroOps = 2;
+ let ResourceCycles = [26, 26]; }
def M3WriteNEONZ : SchedWriteRes<[M3UnitNMSC,
M3UnitNMSC]> { let Latency = 5;
let NumMicroOps = 2; }
@@ -365,50 +365,50 @@ def M3WriteVLDC : SchedWriteRes<[M3Un
def M3WriteVLDD : SchedWriteRes<[M3UnitL,
M3UnitNALU]> { let Latency = 7;
let NumMicroOps = 2;
- let ResourceCycles = [2]; }
+ let ResourceCycles = [2, 1]; }
def M3WriteVLDE : SchedWriteRes<[M3UnitL,
M3UnitNALU]> { let Latency = 6;
let NumMicroOps = 2;
- let ResourceCycles = [2]; }
+ let ResourceCycles = [2, 1]; }
def M3WriteVLDF : SchedWriteRes<[M3UnitL,
M3UnitL]> { let Latency = 10;
let NumMicroOps = 2;
- let ResourceCycles = [5]; }
+ let ResourceCycles = [5, 5]; }
def M3WriteVLDG : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU]> { let Latency = 7;
let NumMicroOps = 3;
- let ResourceCycles = [2]; }
+ let ResourceCycles = [2, 1, 1]; }
def M3WriteVLDH : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU]> { let Latency = 6;
let NumMicroOps = 3;
- let ResourceCycles = [2]; }
+ let ResourceCycles = [2, 1, 1]; }
def M3WriteVLDI : SchedWriteRes<[M3UnitL,
M3UnitL,
M3UnitL]> { let Latency = 12;
let NumMicroOps = 3;
- let ResourceCycles = [6]; }
+ let ResourceCycles = [6, 6, 6]; }
def M3WriteVLDJ : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU,
M3UnitNALU]> { let Latency = 7;
let NumMicroOps = 4;
- let ResourceCycles = [2]; }
+ let ResourceCycles = [2, 1, 1, 1]; }
def M3WriteVLDK : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU,
M3UnitNALU,
M3UnitNALU]> { let Latency = 9;
let NumMicroOps = 5;
- let ResourceCycles = [4]; }
+ let ResourceCycles = [4, 1, 1, 1, 1]; }
def M3WriteVLDL : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU,
M3UnitL,
M3UnitNALU]> { let Latency = 6;
let NumMicroOps = 5;
- let ResourceCycles = [3]; }
+ let ResourceCycles = [6, 1, 1, 6, 1]; }
def M3WriteVLDM : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU,
@@ -416,13 +416,13 @@ def M3WriteVLDM : SchedWriteRes<[M3Un
M3UnitNALU,
M3UnitNALU]> { let Latency = 7;
let NumMicroOps = 6;
- let ResourceCycles = [3]; }
+ let ResourceCycles = [6, 1, 1, 6, 1, 1]; }
def M3WriteVLDN : SchedWriteRes<[M3UnitL,
M3UnitL,
M3UnitL,
M3UnitL]> { let Latency = 14;
let NumMicroOps = 4;
- let ResourceCycles = [7]; }
+ let ResourceCycles = [6, 6, 6, 6]; }
def M3WriteVSTA : WriteSequence<[WriteVST], 2>;
def M3WriteVSTB : WriteSequence<[WriteVST], 3>;
def M3WriteVSTC : WriteSequence<[WriteVST], 4>;
@@ -430,16 +430,16 @@ def M3WriteVSTD : SchedWriteRes<[M3Un
M3UnitFST,
M3UnitS,
M3UnitFST]> { let Latency = 7;
- let NumMicroOps = 2;
- let ResourceCycles = [7]; }
+ let NumMicroOps = 4;
+ let ResourceCycles = [1, 3, 1, 3]; }
def M3WriteVSTE : SchedWriteRes<[M3UnitS,
M3UnitFST,
M3UnitS,
M3UnitFST,
M3UnitS,
M3UnitFST]> { let Latency = 8;
- let NumMicroOps = 3;
- let ResourceCycles = [8]; }
+ let NumMicroOps = 6;
+ let ResourceCycles = [1, 3, 1, 3, 1, 3]; }
def M3WriteVSTF : SchedWriteRes<[M3UnitNALU,
M3UnitFST,
M3UnitFST,
@@ -447,8 +447,8 @@ def M3WriteVSTF : SchedWriteRes<[M3Un
M3UnitFST,
M3UnitS,
M3UnitFST]> { let Latency = 15;
- let NumMicroOps = 5;
- let ResourceCycles = [15]; }
+ let NumMicroOps = 7;
+ let ResourceCycles = [1, 3, 3, 1, 3, 1, 3]; }
def M3WriteVSTG : SchedWriteRes<[M3UnitNALU,
M3UnitFST,
M3UnitFST,
@@ -458,15 +458,15 @@ def M3WriteVSTG : SchedWriteRes<[M3Un
M3UnitFST,
M3UnitS,
M3UnitFST]> { let Latency = 16;
- let NumMicroOps = 6;
- let ResourceCycles = [16]; }
+ let NumMicroOps = 9;
+ let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
def M3WriteVSTH : SchedWriteRes<[M3UnitNALU,
M3UnitFST,
M3UnitFST,
M3UnitS,
M3UnitFST]> { let Latency = 14;
- let NumMicroOps = 4;
- let ResourceCycles = [14]; }
+ let NumMicroOps = 5;
+ let ResourceCycles = [1, 3, 3, 1, 3]; }
def M3WriteVSTI : SchedWriteRes<[M3UnitNALU,
M3UnitFST,
M3UnitFST,
@@ -476,8 +476,8 @@ def M3WriteVSTI : SchedWriteRes<[M3Un
M3UnitFST,
M3UnitS,
M3UnitFST]> { let Latency = 17;
- let NumMicroOps = 7;
- let ResourceCycles = [17]; }
+ let NumMicroOps = 9;
+ let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
// Special cases.
def M3WriteAES : SchedWriteRes<[M3UnitNCRY]> { let Latency = 1; }