[PATCH] D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes.
Renato Golin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri May 18 05:25:34 PDT 2018
rengolin added inline comments.
================
Comment at: include/llvm/Target/TargetInstrPredicate.td:110
+// operand at position `Index` is a register operand.
+class CheckRegOperandValue<int Index, Register R>
+ : MCOperandPredicate<Index> {
----------------
andreadb wrote:
> RKSimon wrote:
> > The use of 'Value' makes is it sound like we need the register to contain a certain value, not that it must be a certain register.
> I am okay with bikeshedding names if people don't like them.
>
> What if I change `CheckRegOperand` into `CheckOperandIsRegister`, and then rename `CheckRegOperandValue` to `CheckRegOperand`?
This would make git archaeology confusing... :)
https://reviews.llvm.org/D46695
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