[llvm] r332617 - [RISCV] Set isReMaterializable on ADDI and LUI instructions
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Thu May 17 08:51:37 PDT 2018
Author: asb
Date: Thu May 17 08:51:37 2018
New Revision: 332617
URL: http://llvm.org/viewvc/llvm-project?rev=332617&view=rev
Log:
[RISCV] Set isReMaterializable on ADDI and LUI instructions
The isReMaterlizable flag is somewhat confusing, unlike most other instruction
flags it is currently interpreted as a hint (mightBeRematerializable would be
a better name). While LUI is always rematerialisable, for an instruction like
ADDI it depends on its operands. TargetInstrInfo::isTriviallyReMaterializable
will call TargetInstrInfo::isReallyTriviallyReMaterializable, which in turn
calls TargetInstrInfo::isReallyTriviallyReMaterializableGeneric. We rely on
the logic in the latter to pick out instances of ADDI that really are
rematerializable.
The isReMaterializable flag does make a difference on a variety of test
programs. The recently committed remat.ll test case demonstrates how stack
usage is reduce and a unnecessary lw/sw can be removed. Stack usage in the
Proc0 function in dhrystone reduces from 192 bytes to 112 bytes.
For the sake of completeness, this patch also implements
RISCVRegisterInfo::isConstantPhysReg. Although this is called from a number of
places, it doesn't seem to result in different codegen for any programs I've
thrown at it. However, it is called in the rematerialisation codepath and it
seems sensible to implement something correct here.
Differential Revision: https://reviews.llvm.org/D46182
Modified:
llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.cpp
llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.h
llvm/trunk/test/CodeGen/RISCV/remat.ll
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td?rev=332617&r1=332616&r2=332617&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td Thu May 17 08:51:37 2018
@@ -267,7 +267,7 @@ class Priv<string opcodestr, bits<7> fun
// Instructions
//===----------------------------------------------------------------------===//
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+let hasSideEffects = 0, isReMaterializable = 1, mayLoad = 0, mayStore = 0 in {
def LUI : RVInstU<OPC_LUI, (outs GPR:$rd), (ins uimm20:$imm20),
"lui", "$rd, $imm20">;
@@ -301,7 +301,11 @@ def SB : Store_rri<0b000, "sb">;
def SH : Store_rri<0b001, "sh">;
def SW : Store_rri<0b010, "sw">;
+// ADDI isn't always rematerializable, but isReMaterializable will be used as
+// a hint which is verified in isReallyTriviallyReMaterializable.
+let isReMaterializable = 1 in
def ADDI : ALU_ri<0b000, "addi">;
+
def SLTI : ALU_ri<0b010, "slti">;
def SLTIU : ALU_ri<0b011, "sltiu">;
def XORI : ALU_ri<0b100, "xori">;
Modified: llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.cpp?rev=332617&r1=332616&r2=332617&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.cpp Thu May 17 08:51:37 2018
@@ -50,6 +50,10 @@ BitVector RISCVRegisterInfo::getReserved
return Reserved;
}
+bool RISCVRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
+ return PhysReg == RISCV::X0;
+}
+
const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
return CSR_NoRegs_RegMask;
}
Modified: llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.h?rev=332617&r1=332616&r2=332617&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.h Thu May 17 08:51:37 2018
@@ -32,6 +32,8 @@ struct RISCVRegisterInfo : public RISCVG
BitVector getReservedRegs(const MachineFunction &MF) const override;
+ bool isConstantPhysReg(unsigned PhysReg) const override;
+
const uint32_t *getNoPreservedMask() const override;
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
Modified: llvm/trunk/test/CodeGen/RISCV/remat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/remat.ll?rev=332617&r1=332616&r2=332617&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/remat.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/remat.ll Thu May 17 08:51:37 2018
@@ -20,36 +20,29 @@
; the stack and restored. It creates high register pressure to force this
; situation.
-; TODO: it makes no sense to spill %hi(h), %hi(l) or the constant 64 to the
-; stack.
-
define i32 @test() nounwind {
; RV32I-LABEL: test:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: addi sp, sp, -64
-; RV32I-NEXT: sw ra, 60(sp)
-; RV32I-NEXT: sw s1, 56(sp)
-; RV32I-NEXT: sw s2, 52(sp)
-; RV32I-NEXT: sw s3, 48(sp)
-; RV32I-NEXT: sw s4, 44(sp)
-; RV32I-NEXT: sw s5, 40(sp)
-; RV32I-NEXT: sw s6, 36(sp)
-; RV32I-NEXT: sw s7, 32(sp)
-; RV32I-NEXT: sw s8, 28(sp)
-; RV32I-NEXT: sw s9, 24(sp)
-; RV32I-NEXT: sw s10, 20(sp)
-; RV32I-NEXT: sw s11, 16(sp)
+; RV32I-NEXT: addi sp, sp, -48
+; RV32I-NEXT: sw ra, 44(sp)
+; RV32I-NEXT: sw s1, 40(sp)
+; RV32I-NEXT: sw s2, 36(sp)
+; RV32I-NEXT: sw s3, 32(sp)
+; RV32I-NEXT: sw s4, 28(sp)
+; RV32I-NEXT: sw s5, 24(sp)
+; RV32I-NEXT: sw s6, 20(sp)
+; RV32I-NEXT: sw s7, 16(sp)
+; RV32I-NEXT: sw s8, 12(sp)
+; RV32I-NEXT: sw s9, 8(sp)
+; RV32I-NEXT: sw s10, 4(sp)
+; RV32I-NEXT: sw s11, 0(sp)
; RV32I-NEXT: lui s3, %hi(a)
; RV32I-NEXT: lw a0, %lo(a)(s3)
; RV32I-NEXT: beqz a0, .LBB0_11
; RV32I-NEXT: # %bb.1: # %for.body.preheader
-; RV32I-NEXT: lui a1, %hi(l)
-; RV32I-NEXT: sw a1, 12(sp)
; RV32I-NEXT: lui s5, %hi(k)
; RV32I-NEXT: lui s6, %hi(j)
; RV32I-NEXT: lui s7, %hi(i)
-; RV32I-NEXT: lui a1, %hi(h)
-; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: lui s9, %hi(g)
; RV32I-NEXT: lui s10, %hi(f)
; RV32I-NEXT: lui s11, %hi(e)
@@ -57,11 +50,9 @@ define i32 @test() nounwind {
; RV32I-NEXT: addi s1, zero, 32
; RV32I-NEXT: lui s2, %hi(c)
; RV32I-NEXT: lui s4, %hi(b)
-; RV32I-NEXT: addi a1, zero, 64
-; RV32I-NEXT: sw a1, 4(sp)
; RV32I-NEXT: .LBB0_2: # %for.body
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: lw a1, 12(sp)
+; RV32I-NEXT: lui a1, %hi(l)
; RV32I-NEXT: lw a1, %lo(l)(a1)
; RV32I-NEXT: beqz a1, .LBB0_4
; RV32I-NEXT: # %bb.3: # %if.then
@@ -83,7 +74,7 @@ define i32 @test() nounwind {
; RV32I-NEXT: lw a2, %lo(d)(s8)
; RV32I-NEXT: lw a1, %lo(c)(s2)
; RV32I-NEXT: lw a0, %lo(b)(s4)
-; RV32I-NEXT: lw a5, 4(sp)
+; RV32I-NEXT: addi a5, zero, 64
; RV32I-NEXT: call foo
; RV32I-NEXT: .LBB0_6: # %if.end5
; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1
@@ -104,7 +95,7 @@ define i32 @test() nounwind {
; RV32I-NEXT: beqz a0, .LBB0_10
; RV32I-NEXT: # %bb.9: # %if.then11
; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1
-; RV32I-NEXT: lw a0, 8(sp)
+; RV32I-NEXT: lui a0, %hi(h)
; RV32I-NEXT: lw a4, %lo(h)(a0)
; RV32I-NEXT: lw a3, %lo(g)(s9)
; RV32I-NEXT: lw a2, %lo(f)(s10)
@@ -120,19 +111,19 @@ define i32 @test() nounwind {
; RV32I-NEXT: bnez a0, .LBB0_2
; RV32I-NEXT: .LBB0_11: # %for.end
; RV32I-NEXT: addi a0, zero, 1
-; RV32I-NEXT: lw s11, 16(sp)
-; RV32I-NEXT: lw s10, 20(sp)
-; RV32I-NEXT: lw s9, 24(sp)
-; RV32I-NEXT: lw s8, 28(sp)
-; RV32I-NEXT: lw s7, 32(sp)
-; RV32I-NEXT: lw s6, 36(sp)
-; RV32I-NEXT: lw s5, 40(sp)
-; RV32I-NEXT: lw s4, 44(sp)
-; RV32I-NEXT: lw s3, 48(sp)
-; RV32I-NEXT: lw s2, 52(sp)
-; RV32I-NEXT: lw s1, 56(sp)
-; RV32I-NEXT: lw ra, 60(sp)
-; RV32I-NEXT: addi sp, sp, 64
+; RV32I-NEXT: lw s11, 0(sp)
+; RV32I-NEXT: lw s10, 4(sp)
+; RV32I-NEXT: lw s9, 8(sp)
+; RV32I-NEXT: lw s8, 12(sp)
+; RV32I-NEXT: lw s7, 16(sp)
+; RV32I-NEXT: lw s6, 20(sp)
+; RV32I-NEXT: lw s5, 24(sp)
+; RV32I-NEXT: lw s4, 28(sp)
+; RV32I-NEXT: lw s3, 32(sp)
+; RV32I-NEXT: lw s2, 36(sp)
+; RV32I-NEXT: lw s1, 40(sp)
+; RV32I-NEXT: lw ra, 44(sp)
+; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
entry:
%.pr = load i32, i32* @a, align 4
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