[llvm] r332605 - [X86] Split WriteADC/WriteADCRMW scheduler classes
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu May 17 05:43:43 PDT 2018
Author: rksimon
Date: Thu May 17 05:43:42 2018
New Revision: 332605
URL: http://llvm.org/viewvc/llvm-project?rev=332605&view=rev
Log:
[X86] Split WriteADC/WriteADCRMW scheduler classes
For integer ALU instructions taking eflags as an input (ADC/SBB/ADCX/ADOX)
Modified:
llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/lib/Target/X86/X86Schedule.td
llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
llvm/trunk/test/CodeGen/X86/adx-schedule.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrArithmetic.td?rev=332605&r1=332604&r2=332605&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrArithmetic.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrArithmetic.td Thu May 17 05:43:42 2018
@@ -627,17 +627,17 @@ class ITy<bits<8> opcode, Format f, X86T
// BinOpRR - Instructions like "add reg, reg, reg".
class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
- dag outlist, list<dag> pattern>
+ dag outlist, X86FoldableSchedWrite sched, list<dag> pattern>
: ITy<opcode, MRMDestReg, typeinfo, outlist,
(ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
- Sched<[WriteALU]>;
+ Sched<[sched]>;
// BinOpRR_F - Instructions like "cmp reg, Reg", where the pattern has
// just a EFLAGS as a result.
class BinOpRR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
SDPatternOperator opnode>
- : BinOpRR<opcode, mnemonic, typeinfo, (outs),
+ : BinOpRR<opcode, mnemonic, typeinfo, (outs), WriteALU,
[(set EFLAGS,
(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
@@ -645,7 +645,7 @@ class BinOpRR_F<bits<8> opcode, string m
// both a regclass and EFLAGS as a result.
class BinOpRR_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
SDNode opnode>
- : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
+ : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteALU,
[(set typeinfo.RegClass:$dst, EFLAGS,
(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
@@ -653,18 +653,19 @@ class BinOpRR_RF<bits<8> opcode, string
// both a regclass and EFLAGS as a result, and has EFLAGS as input.
class BinOpRR_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
SDNode opnode>
- : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
+ : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteADC,
[(set typeinfo.RegClass:$dst, EFLAGS,
(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
EFLAGS))]>;
// BinOpRR_Rev - Instructions like "add reg, reg, reg" (reversed encoding).
-class BinOpRR_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
+class BinOpRR_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
+ X86FoldableSchedWrite sched = WriteALU>
: ITy<opcode, MRMSrcReg, typeinfo,
(outs typeinfo.RegClass:$dst),
(ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
mnemonic, "{$src2, $dst|$dst, $src2}", []>,
- Sched<[WriteALU]> {
+ Sched<[sched]> {
// The disassembler should know about this, but not the asmparser.
let isCodeGenOnly = 1;
let ForceDisassemble = 1;
@@ -673,7 +674,7 @@ class BinOpRR_Rev<bits<8> opcode, string
// BinOpRR_RDD_Rev - Instructions like "adc reg, reg, reg" (reversed encoding).
class BinOpRR_RFF_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
- : BinOpRR_Rev<opcode, mnemonic, typeinfo>;
+ : BinOpRR_Rev<opcode, mnemonic, typeinfo, WriteADC>;
// BinOpRR_F_Rev - Instructions like "cmp reg, reg" (reversed encoding).
class BinOpRR_F_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
@@ -689,93 +690,93 @@ class BinOpRR_F_Rev<bits<8> opcode, stri
// BinOpRM - Instructions like "add reg, reg, [mem]".
class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
- dag outlist, list<dag> pattern>
+ dag outlist, X86FoldableSchedWrite sched, list<dag> pattern>
: ITy<opcode, MRMSrcMem, typeinfo, outlist,
(ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
- Sched<[WriteALULd, ReadAfterLd]>;
+ Sched<[sched.Folded, ReadAfterLd]>;
// BinOpRM_F - Instructions like "cmp reg, [mem]".
class BinOpRM_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
SDNode opnode>
- : BinOpRM<opcode, mnemonic, typeinfo, (outs),
+ : BinOpRM<opcode, mnemonic, typeinfo, (outs), WriteALU,
[(set EFLAGS,
(opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
// BinOpRM_RF - Instructions like "add reg, reg, [mem]".
class BinOpRM_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
SDNode opnode>
- : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
+ : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteALU,
[(set typeinfo.RegClass:$dst, EFLAGS,
(opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
// BinOpRM_RFF - Instructions like "adc reg, reg, [mem]".
class BinOpRM_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
SDNode opnode>
- : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
+ : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteADC,
[(set typeinfo.RegClass:$dst, EFLAGS,
(opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2),
EFLAGS))]>;
// BinOpRI - Instructions like "add reg, reg, imm".
class BinOpRI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
- Format f, dag outlist, list<dag> pattern>
+ Format f, dag outlist, X86FoldableSchedWrite sched, list<dag> pattern>
: ITy<opcode, f, typeinfo, outlist,
(ins typeinfo.RegClass:$src1, typeinfo.ImmOperand:$src2),
mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
- Sched<[WriteALU]> {
+ Sched<[sched]> {
let ImmT = typeinfo.ImmEncoding;
}
// BinOpRI_F - Instructions like "cmp reg, imm".
class BinOpRI_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
SDPatternOperator opnode, Format f>
- : BinOpRI<opcode, mnemonic, typeinfo, f, (outs),
+ : BinOpRI<opcode, mnemonic, typeinfo, f, (outs), WriteALU,
[(set EFLAGS,
(opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
// BinOpRI_RF - Instructions like "add reg, reg, imm".
class BinOpRI_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
SDNode opnode, Format f>
- : BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
+ : BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), WriteALU,
[(set typeinfo.RegClass:$dst, EFLAGS,
(opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
// BinOpRI_RFF - Instructions like "adc reg, reg, imm".
class BinOpRI_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
SDNode opnode, Format f>
- : BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
+ : BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), WriteADC,
[(set typeinfo.RegClass:$dst, EFLAGS,
(opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2,
EFLAGS))]>;
// BinOpRI8 - Instructions like "add reg, reg, imm8".
class BinOpRI8<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
- Format f, dag outlist, list<dag> pattern>
+ Format f, dag outlist, X86FoldableSchedWrite sched, list<dag> pattern>
: ITy<opcode, f, typeinfo, outlist,
(ins typeinfo.RegClass:$src1, typeinfo.Imm8Operand:$src2),
mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
- Sched<[WriteALU]> {
+ Sched<[sched]> {
let ImmT = Imm8; // Always 8-bit immediate.
}
// BinOpRI8_F - Instructions like "cmp reg, imm8".
class BinOpRI8_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
SDPatternOperator opnode, Format f>
- : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs),
+ : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs), WriteALU,
[(set EFLAGS,
(opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
// BinOpRI8_RF - Instructions like "add reg, reg, imm8".
class BinOpRI8_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
SDPatternOperator opnode, Format f>
- : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
+ : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), WriteALU,
[(set typeinfo.RegClass:$dst, EFLAGS,
(opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
// BinOpRI8_RFF - Instructions like "adc reg, reg, imm8".
class BinOpRI8_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
SDPatternOperator opnode, Format f>
- : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
+ : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), WriteADC,
[(set typeinfo.RegClass:$dst, EFLAGS,
(opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2,
EFLAGS))]>;
@@ -800,7 +801,7 @@ class BinOpMR_RMW_FF<bits<8> opcode, str
: BinOpMR<opcode, mnemonic, typeinfo,
[(store (opnode (load addr:$dst), typeinfo.RegClass:$src, EFLAGS),
addr:$dst),
- (implicit EFLAGS)]>, Sched<[WriteALURMW]>;
+ (implicit EFLAGS)]>, Sched<[WriteADCRMW]>;
// BinOpMR_F - Instructions like "cmp [mem], reg".
class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
@@ -833,7 +834,7 @@ class BinOpMI_RMW_FF<bits<8> opcode, str
: BinOpMI<opcode, mnemonic, typeinfo, f,
[(store (opnode (typeinfo.VT (load addr:$dst)),
typeinfo.ImmOperator:$src, EFLAGS), addr:$dst),
- (implicit EFLAGS)]>, Sched<[WriteALURMW]>;
+ (implicit EFLAGS)]>, Sched<[WriteADCRMW]>;
// BinOpMI_F - Instructions like "cmp [mem], imm".
class BinOpMI_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
@@ -866,7 +867,7 @@ class BinOpMI8_RMW_FF<string mnemonic, X
: BinOpMI8<mnemonic, typeinfo, f,
[(store (opnode (load addr:$dst),
typeinfo.Imm8Operator:$src, EFLAGS), addr:$dst),
- (implicit EFLAGS)]>, Sched<[WriteALURMW]>;
+ (implicit EFLAGS)]>, Sched<[WriteADCRMW]>;
// BinOpMI8_F - Instructions like "cmp [mem], imm8".
class BinOpMI8_F<string mnemonic, X86TypeInfo typeinfo,
@@ -878,10 +879,10 @@ class BinOpMI8_F<string mnemonic, X86Typ
// BinOpAI - Instructions like "add %eax, %eax, imm", that imp-def EFLAGS.
class BinOpAI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
- Register areg, string operands>
+ Register areg, string operands, X86FoldableSchedWrite sched = WriteALU>
: ITy<opcode, RawFrm, typeinfo,
(outs), (ins typeinfo.ImmOperand:$src),
- mnemonic, operands, []>, Sched<[WriteALU]> {
+ mnemonic, operands, []>, Sched<[sched]> {
let ImmT = typeinfo.ImmEncoding;
let Uses = [areg];
let Defs = [areg, EFLAGS];
@@ -892,7 +893,7 @@ class BinOpAI<bits<8> opcode, string mne
// and use EFLAGS.
class BinOpAI_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
Register areg, string operands>
- : BinOpAI<opcode, mnemonic, typeinfo, areg, operands> {
+ : BinOpAI<opcode, mnemonic, typeinfo, areg, operands, WriteADC> {
let Uses = [areg, EFLAGS];
}
@@ -1287,7 +1288,7 @@ let Predicates = [HasBMI2] in {
//
let Predicates = [HasADX], Defs = [EFLAGS], Uses = [EFLAGS],
Constraints = "$src1 = $dst", AddedComplexity = 10 in {
- let SchedRW = [WriteALU] in {
+ let SchedRW = [WriteADC] in {
def ADCX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst),
(ins GR32:$src1, GR32:$src2),
"adcx{l}\t{$src2, $dst|$dst, $src2}",
@@ -1311,7 +1312,7 @@ let Predicates = [HasADX], Defs = [EFLAG
} // hasSideEffects = 0
} // SchedRW
- let mayLoad = 1, SchedRW = [WriteALULd, ReadAfterLd] in {
+ let mayLoad = 1, SchedRW = [WriteADCLd, ReadAfterLd] in {
def ADCX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst),
(ins GR32:$src1, i32mem:$src2),
"adcx{l}\t{$src2, $dst|$dst, $src2}",
@@ -1336,5 +1337,5 @@ let Predicates = [HasADX], Defs = [EFLAG
(ins GR64:$src1, i64mem:$src2),
"adox{q}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
} // hasSideEffects = 0
- } // mayLoad = 1, SchedRW = [WriteALULd]
+ } // mayLoad = 1, SchedRW = [WriteADCLd]
}
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=332605&r1=332604&r2=332605&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Thu May 17 05:43:42 2018
@@ -107,6 +107,7 @@ def : WriteRes<WriteRMW, [BWPort237,BWPo
// Arithmetic.
defm : BWWriteResPair<WriteALU, [BWPort0156], 1>; // Simple integer ALU op.
+defm : BWWriteResPair<WriteADC, [BWPort06], 1>; // Integer ALU + flags op.
defm : BWWriteResPair<WriteIMul, [BWPort1], 3>; // Integer multiplication.
defm : BWWriteResPair<WriteIMul64, [BWPort1], 3>; // Integer 64-bit multiplication.
@@ -552,22 +553,14 @@ def BWWriteResGroup6 : SchedWriteRes<[BW
let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>;
-def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
- "ADC(16|32|64)i",
- "ADC(8|16|32|64)rr",
- "ADCX(32|64)rr",
- "ADOX(32|64)rr",
- "BT(16|32|64)ri8",
+def: InstRW<[BWWriteResGroup6], (instregex "BT(16|32|64)ri8",
"BT(16|32|64)rr",
"BTC(16|32|64)ri8",
"BTC(16|32|64)rr",
"BTR(16|32|64)ri8",
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
- "BTS(16|32|64)rr",
- "SBB(16|32|64)ri",
- "SBB(16|32|64)i",
- "SBB(8|16|32|64)rr")>;
+ "BTS(16|32|64)rr")>;
def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
let Latency = 1;
@@ -1010,10 +1003,6 @@ def BWWriteResGroup63 : SchedWriteRes<[B
let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup63], (instregex "BT(16|32|64)mi8")>;
-def: InstRW<[BWWriteResGroup63, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
- ADCX32rm, ADCX64rm,
- ADOX32rm, ADOX64rm,
- SBB8rm, SBB16rm, SBB32rm, SBB64rm)>;
def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
let Latency = 6;
@@ -1246,15 +1235,12 @@ def BWWriteResGroup100 : SchedWriteRes<[
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,2,1];
}
-def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mi",
- "CMPXCHG(8|16|32|64)rm",
+def : SchedAlias<WriteADCRMW, BWWriteResGroup100>;
+def: InstRW<[BWWriteResGroup100], (instregex "CMPXCHG(8|16|32|64)rm",
"ROL(8|16|32|64)mCL",
"SAR(8|16|32|64)mCL",
- "SBB(8|16|32|64)mi",
"SHL(8|16|32|64)mCL",
"SHR(8|16|32|64)mCL")>;
-def: InstRW<[BWWriteResGroup100, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr,
- SBB8mr, SBB16mr, SBB32mr, SBB64mr)>;
def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
let Latency = 9;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=332605&r1=332604&r2=332605&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Thu May 17 05:43:42 2018
@@ -114,6 +114,7 @@ defm : X86WriteRes<WriteMove, [HWPort
def : WriteRes<WriteZero, []>;
defm : HWWriteResPair<WriteALU, [HWPort0156], 1>;
+defm : HWWriteResPair<WriteADC, [HWPort06,HWPort0156], 2, [1,1], 2>;
defm : HWWriteResPair<WriteIMul, [HWPort1], 3>;
defm : HWWriteResPair<WriteIMul64, [HWPort1], 3>;
def : WriteRes<WriteIMulH, []> { let Latency = 3; }
@@ -1134,13 +1135,7 @@ def HWWriteResGroup35 : SchedWriteRes<[H
let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup35], (instrs CWD, JCXZ, JECXZ, JRCXZ)>;
-def: InstRW<[HWWriteResGroup35], (instregex "ADC(8|16|32|64)ri",
- "ADC(8|16|32|64)rr",
- "ADC(8|16|32|64)i",
- "SBB(8|16|32|64)ri",
- "SBB(8|16|32|64)rr",
- "SBB(8|16|32|64)i",
- "SET(A|BE)r")>;
+def: InstRW<[HWWriteResGroup35], (instregex "SET(A|BE)r")>;
def HWWriteResGroup36_2 : SchedWriteRes<[HWPort5,HWPort23]> {
let Latency = 7;
@@ -1173,14 +1168,6 @@ def HWWriteResGroup41 : SchedWriteRes<[H
}
def: InstRW<[HWWriteResGroup41], (instrs LRETQ, RETL, RETQ)>;
-def HWWriteResGroup43 : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> {
- let Latency = 7;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[HWWriteResGroup43, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
- SBB8rm, SBB16rm, SBB32rm, SBB64rm)>;
-
def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> {
let Latency = 3;
let NumMicroOps = 4;
@@ -1374,15 +1361,12 @@ def HWWriteResGroup69 : SchedWriteRes<[H
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,2,1];
}
-def: InstRW<[HWWriteResGroup69], (instregex "ADC(8|16|32|64)mi",
- "CMPXCHG(8|16|32|64)rm",
+def: InstRW<[HWWriteResGroup69], (instregex "CMPXCHG(8|16|32|64)rm",
"ROL(8|16|32|64)mCL",
"SAR(8|16|32|64)mCL",
- "SBB(8|16|32|64)mi",
"SHL(8|16|32|64)mCL",
"SHR(8|16|32|64)mCL")>;
-def: InstRW<[HWWriteResGroup69, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr,
- SBB8mr, SBB16mr, SBB32mr, SBB64mr)>;
+def: SchedAlias<WriteADCRMW, HWWriteResGroup69>;
def HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort1]> {
let Latency = 4;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=332605&r1=332604&r2=332605&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Thu May 17 05:43:42 2018
@@ -103,6 +103,7 @@ def : WriteRes<WriteMove, [SBPort015]
def : WriteRes<WriteZero, []>;
defm : SBWriteResPair<WriteALU, [SBPort015], 1>;
+defm : SBWriteResPair<WriteADC, [SBPort05,SBPort015], 2, [1,1], 2>;
defm : SBWriteResPair<WriteIMul, [SBPort1], 3>;
defm : SBWriteResPair<WriteIMul64, [SBPort1], 3>;
@@ -606,13 +607,7 @@ def SBWriteResGroup19 : SchedWriteRes<[S
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup19], (instregex "ADC(8|16|32|64)ri",
- "ADC(8|16|32|64)rr",
- "ADC(8|16|32|64)i",
- "SBB(8|16|32|64)ri",
- "SBB(8|16|32|64)rr",
- "SBB(8|16|32|64)i",
- "SHLD(16|32|64)rri8",
+def: InstRW<[SBWriteResGroup19], (instregex "SHLD(16|32|64)rri8",
"SHRD(16|32|64)rri8")>;
def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> {
@@ -917,14 +912,6 @@ def SBWriteResGroup64 : SchedWriteRes<[S
}
def: InstRW<[SBWriteResGroup64], (instrs FARJMP64)>;
-def SBWriteResGroup65 : SchedWriteRes<[SBPort23,SBPort05,SBPort015]> {
- let Latency = 7;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SBWriteResGroup65, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
- SBB8rm, SBB16rm, SBB32rm, SBB64rm)>;
-
def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> {
let Latency = 7;
let NumMicroOps = 4;
@@ -1101,8 +1088,7 @@ def SBWriteResGroup98 : SchedWriteRes<[S
let NumMicroOps = 6;
let ResourceCycles = [1,2,3];
}
-def: InstRW<[SBWriteResGroup98], (instregex "ADC(8|16|32|64)mi",
- "SBB(8|16|32|64)mi")>;
+def: SchedAlias<WriteADCRMW, SBWriteResGroup98>;
def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> {
let Latency = 9;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=332605&r1=332604&r2=332605&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Thu May 17 05:43:42 2018
@@ -106,6 +106,7 @@ def : WriteRes<WriteRMW, [SKLPort237,SKL
// Arithmetic.
defm : SKLWriteResPair<WriteALU, [SKLPort0156], 1>; // Simple integer ALU op.
+defm : SKLWriteResPair<WriteADC, [SKLPort06], 1>; // Integer ALU + flags op.
defm : SKLWriteResPair<WriteIMul, [SKLPort1], 3>; // Integer multiplication.
defm : SKLWriteResPair<WriteIMul64, [SKLPort1], 3>; // Integer 64-bit multiplication.
@@ -551,22 +552,14 @@ def SKLWriteResGroup7 : SchedWriteRes<[S
let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
-def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri",
- "ADC(16|32|64)i",
- "ADC(8|16|32|64)rr",
- "ADCX(32|64)rr",
- "ADOX(32|64)rr",
- "BT(16|32|64)ri8",
+def: InstRW<[SKLWriteResGroup7], (instregex "BT(16|32|64)ri8",
"BT(16|32|64)rr",
"BTC(16|32|64)ri8",
"BTC(16|32|64)rr",
"BTR(16|32|64)ri8",
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
- "BTS(16|32|64)rr",
- "SBB(16|32|64)ri",
- "SBB(16|32|64)i",
- "SBB(8|16|32|64)rr")>;
+ "BTS(16|32|64)rr")>;
def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
let Latency = 1;
@@ -1059,10 +1052,6 @@ def SKLWriteResGroup74 : SchedWriteRes<[
let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8")>;
-def: InstRW<[SKLWriteResGroup74, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
- ADCX32rm, ADCX64rm,
- ADOX32rm, ADOX64rm,
- SBB8rm, SBB16rm, SBB32rm, SBB64rm)>;
def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
let Latency = 6;
@@ -1349,11 +1338,8 @@ def SKLWriteResGroup119 : SchedWriteRes<
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,2,1];
}
-def: InstRW<[SKLWriteResGroup119], (instregex "ADC(8|16|32|64)mi",
- "CMPXCHG(8|16|32|64)rm",
- "SBB(8|16|32|64)mi")>;
-def: InstRW<[SKLWriteResGroup119, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr,
- SBB8mr, SBB16mr, SBB32mr, SBB64mr)>;
+def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>;
+def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG(8|16|32|64)rm")>;
def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 9;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=332605&r1=332604&r2=332605&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Thu May 17 05:43:42 2018
@@ -106,6 +106,7 @@ def : WriteRes<WriteRMW, [SKXPort237,SKX
// Arithmetic.
defm : SKXWriteResPair<WriteALU, [SKXPort0156], 1>; // Simple integer ALU op.
+defm : SKXWriteResPair<WriteADC, [SKXPort06], 1>; // Integer ALU + flags op.
defm : SKXWriteResPair<WriteIMul, [SKXPort1], 3>; // Integer multiplication.
defm : SKXWriteResPair<WriteIMul64, [SKXPort1], 3>; // Integer 64-bit multiplication.
@@ -565,22 +566,14 @@ def SKXWriteResGroup7 : SchedWriteRes<[S
let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
-def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri",
- "ADC(16|32|64)i",
- "ADC(8|16|32|64)rr",
- "ADCX(32|64)rr",
- "ADOX(32|64)rr",
- "BT(16|32|64)ri8",
+def: InstRW<[SKXWriteResGroup7], (instregex "BT(16|32|64)ri8",
"BT(16|32|64)rr",
"BTC(16|32|64)ri8",
"BTC(16|32|64)rr",
"BTR(16|32|64)ri8",
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
- "BTS(16|32|64)rr",
- "SBB(16|32|64)ri",
- "SBB(16|32|64)i",
- "SBB(8|16|32|64)rr")>;
+ "BTS(16|32|64)rr")>;
def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {
let Latency = 1;
@@ -1221,10 +1214,6 @@ def SKXWriteResGroup78 : SchedWriteRes<[
let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8")>;
-def: InstRW<[SKXWriteResGroup78, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
- ADCX32rm, ADCX64rm,
- ADOX32rm, ADOX64rm,
- SBB8rm, SBB16rm, SBB32rm, SBB64rm)>;
def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> {
let Latency = 6;
@@ -1687,11 +1676,8 @@ def SKXWriteResGroup130 : SchedWriteRes<
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,2,1];
}
-def: InstRW<[SKXWriteResGroup130], (instregex "ADC(8|16|32|64)mi",
- "CMPXCHG(8|16|32|64)rm",
- "SBB(8|16|32|64)mi")>;
-def: InstRW<[SKXWriteResGroup130, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr,
- SBB8mr, SBB16mr, SBB32mr, SBB64mr)>;
+def: SchedAlias<WriteADCRMW, SKXWriteResGroup130>;
+def: InstRW<[SKXWriteResGroup130], (instregex "CMPXCHG(8|16|32|64)rm")>;
def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
let Latency = 8;
Modified: llvm/trunk/lib/Target/X86/X86Schedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Schedule.td?rev=332605&r1=332604&r2=332605&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Schedule.td (original)
+++ llvm/trunk/lib/Target/X86/X86Schedule.td Thu May 17 05:43:42 2018
@@ -97,7 +97,9 @@ def WriteMove : SchedWrite;
// Arithmetic.
defm WriteALU : X86SchedWritePair; // Simple integer ALU op.
+defm WriteADC : X86SchedWritePair; // Integer ALU + flags op.
def WriteALURMW : WriteSequence<[WriteALULd, WriteStore]>;
+def WriteADCRMW : WriteSequence<[WriteADCLd, WriteStore]>;
defm WriteIMul : X86SchedWritePair; // Integer multiplication.
defm WriteIMul64 : X86SchedWritePair; // Integer 64-bit multiplication.
def WriteIMulH : SchedWrite; // Integer multiplication, high part.
Modified: llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleAtom.td?rev=332605&r1=332604&r2=332605&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleAtom.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleAtom.td Thu May 17 05:43:42 2018
@@ -77,6 +77,7 @@ def : WriteRes<WriteRMW, [AtomPort0]>;
////////////////////////////////////////////////////////////////////////////////
defm : AtomWriteResPair<WriteALU, [AtomPort01], [AtomPort0]>;
+defm : AtomWriteResPair<WriteADC, [AtomPort01], [AtomPort0]>;
defm : AtomWriteResPair<WriteIMul, [AtomPort01], [AtomPort01], 7, 7, [7], [7]>;
defm : AtomWriteResPair<WriteIMul64, [AtomPort01], [AtomPort01], 12, 12, [12], [12]>;
@@ -433,8 +434,6 @@ def AtomWrite0_1 : SchedWriteRes<[AtomPo
}
def : InstRW<[AtomWrite0_1], (instrs FXAM, LD_Frr,
BSWAP32r, BSWAP64r,
- DEC8m, DEC16m, DEC32m, DEC64m,
- INC8m, INC16m, INC32m, INC64m,
MOVSX64rr32,
MMX_MOVD64rr,
MMX_MOVD64to64rr,
@@ -442,8 +441,9 @@ def : InstRW<[AtomWrite0_1], (instrs FXA
MOVDI2SSrr,
MOV64toPQIrr,
MOV64toSDrr)>;
-def : InstRW<[AtomWrite0_1], (instregex "(ADC|ADD|AND|NEG|NOT|OR|SBB|SUB|XOR)(8|16|32|64)m",
- "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
+def : SchedAlias<WriteALURMW, AtomWrite0_1>;
+def : SchedAlias<WriteADCRMW, AtomWrite0_1>;
+def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
"MOV(S|Z)X(32|64)rr(8|8_NOREX|16)")>;
def AtomWrite0_3 : SchedWriteRes<[AtomPort0]> {
Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=332605&r1=332604&r2=332605&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Thu May 17 05:43:42 2018
@@ -156,6 +156,7 @@ def : WriteRes<WriteRMW, [JSAGU]>;
////////////////////////////////////////////////////////////////////////////////
defm : JWriteResIntPair<WriteALU, [JALU01], 1>;
+defm : JWriteResIntPair<WriteADC, [JALU01], 1>;
defm : JWriteResIntPair<WriteIMul, [JALU1, JMul], 3, [1, 1], 2>; // i8/i16/i32 multiplication
defm : JWriteResIntPair<WriteIMul64, [JALU1, JMul], 6, [1, 4], 2>; // i64 multiplication
defm : X86WriteRes<WriteIMulH, [JALU1], 6, [4], 1>;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleSLM.td?rev=332605&r1=332604&r2=332605&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleSLM.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleSLM.td Thu May 17 05:43:42 2018
@@ -94,6 +94,7 @@ def : WriteRes<WriteLDMXCSR, [SLM_MEC_R
def : InstRW<[WriteMove], (instrs COPY)>;
defm : SLMWriteResPair<WriteALU, [SLM_IEC_RSV01], 1>;
+defm : SLMWriteResPair<WriteADC, [SLM_IEC_RSV01], 1>;
defm : SLMWriteResPair<WriteIMul, [SLM_IEC_RSV1], 3>;
defm : SLMWriteResPair<WriteIMul64, [SLM_IEC_RSV1], 3>;
defm : SLMWriteResPair<WriteShift, [SLM_IEC_RSV0], 1>;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=332605&r1=332604&r2=332605&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Thu May 17 05:43:42 2018
@@ -151,6 +151,7 @@ def : WriteRes<WriteLoad, [ZnAGU]> {
def : WriteRes<WriteZero, []>;
def : WriteRes<WriteLEA, [ZnALU]>;
defm : ZnWriteResPair<WriteALU, [ZnALU], 1>;
+defm : ZnWriteResPair<WriteADC, [ZnALU], 1>;
defm : ZnWriteResPair<WriteIMul, [ZnALU1, ZnMultiplier], 4>;
defm : ZnWriteResPair<WriteIMul64, [ZnALU1, ZnMultiplier], 4, [1,1], 2>;
defm : ZnWriteResPair<WriteShift, [ZnALU], 1>;
Modified: llvm/trunk/test/CodeGen/X86/adx-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/adx-schedule.ll?rev=332605&r1=332604&r2=332605&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/adx-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/adx-schedule.ll Thu May 17 05:43:42 2018
@@ -10,10 +10,10 @@ define void @test_adcx(i32 %a0, i32* %a1
; GENERIC-LABEL: test_adcx:
; GENERIC: # %bb.0:
; GENERIC-NEXT: #APP
-; GENERIC-NEXT: adcxl %edi, %edi # sched: [1:0.33]
-; GENERIC-NEXT: adcxq %rdx, %rdx # sched: [1:0.33]
-; GENERIC-NEXT: adcxl (%rsi), %edi # sched: [6:0.50]
-; GENERIC-NEXT: adcxq (%rcx), %rdx # sched: [6:0.50]
+; GENERIC-NEXT: adcxl %edi, %edi # sched: [2:0.67]
+; GENERIC-NEXT: adcxq %rdx, %rdx # sched: [2:0.67]
+; GENERIC-NEXT: adcxl (%rsi), %edi # sched: [7:0.67]
+; GENERIC-NEXT: adcxq (%rcx), %rdx # sched: [7:0.67]
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -40,10 +40,10 @@ define void @test_adcx(i32 %a0, i32* %a1
; KNL-LABEL: test_adcx:
; KNL: # %bb.0:
; KNL-NEXT: #APP
-; KNL-NEXT: adcxl %edi, %edi # sched: [1:0.25]
-; KNL-NEXT: adcxq %rdx, %rdx # sched: [1:0.25]
-; KNL-NEXT: adcxl (%rsi), %edi # sched: [6:0.50]
-; KNL-NEXT: adcxq (%rcx), %rdx # sched: [6:0.50]
+; KNL-NEXT: adcxl %edi, %edi # sched: [2:0.50]
+; KNL-NEXT: adcxq %rdx, %rdx # sched: [2:0.50]
+; KNL-NEXT: adcxl (%rsi), %edi # sched: [7:0.50]
+; KNL-NEXT: adcxq (%rcx), %rdx # sched: [7:0.50]
; KNL-NEXT: #NO_APP
; KNL-NEXT: retq # sched: [7:1.00]
;
@@ -63,10 +63,10 @@ define void @test_adox(i32 %a0, i32* %a1
; GENERIC-LABEL: test_adox:
; GENERIC: # %bb.0:
; GENERIC-NEXT: #APP
-; GENERIC-NEXT: adoxl %edi, %edi # sched: [1:0.33]
-; GENERIC-NEXT: adoxq %rdx, %rdx # sched: [1:0.33]
-; GENERIC-NEXT: adoxl (%rsi), %edi # sched: [6:0.50]
-; GENERIC-NEXT: adoxq (%rcx), %rdx # sched: [6:0.50]
+; GENERIC-NEXT: adoxl %edi, %edi # sched: [2:0.67]
+; GENERIC-NEXT: adoxq %rdx, %rdx # sched: [2:0.67]
+; GENERIC-NEXT: adoxl (%rsi), %edi # sched: [7:0.67]
+; GENERIC-NEXT: adoxq (%rcx), %rdx # sched: [7:0.67]
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -93,10 +93,10 @@ define void @test_adox(i32 %a0, i32* %a1
; KNL-LABEL: test_adox:
; KNL: # %bb.0:
; KNL-NEXT: #APP
-; KNL-NEXT: adoxl %edi, %edi # sched: [1:0.25]
-; KNL-NEXT: adoxq %rdx, %rdx # sched: [1:0.25]
-; KNL-NEXT: adoxl (%rsi), %edi # sched: [6:0.50]
-; KNL-NEXT: adoxq (%rcx), %rdx # sched: [6:0.50]
+; KNL-NEXT: adoxl %edi, %edi # sched: [2:0.50]
+; KNL-NEXT: adoxq %rdx, %rdx # sched: [2:0.50]
+; KNL-NEXT: adoxl (%rsi), %edi # sched: [7:0.50]
+; KNL-NEXT: adoxq (%rcx), %rdx # sched: [7:0.50]
; KNL-NEXT: #NO_APP
; KNL-NEXT: retq # sched: [7:1.00]
;
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