[PATCH] D46989: [RISCV] Separate base from offset in lowerGlobalAddress

[Sameer AbuAsal via Phabricator via llvm-commits]

sabuasal created this revision.
Herald added subscribers: mgrang, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, jordy.potman.lists, simoncook, johnrusso, rbar.

When lowering global address, lower the base as a TargetGlobal first then

  create an SDNode for the offset separately and chain it to the address calculation
      
  This optimization will create a DAG where the base address of a global access will
  be reused between different access. The offset can later be folded into the immediate
  part of the memory access instruction.
      
  With this optimization we generate:
      
  lui a0, %hi(s)
  addi a0, a0, %lo(s) ; shared base address.
      
  addi a1, zero, 20 ; 2 instructions per access.
  sw a1, 44(a0)
      
  addi a1, zero, 10
  sw a1, 8(a0)
      
  addi a1, zero, 30
  sw a1, 80(a0)
      
  Instead of:
      
  lui a0, %hi(s+44) ; 3 instructions per access.
  addi a1, zero, 20
  sw a1, %lo(s+44)(a0)
      
  lui a0, %hi(s+8)
  addi a1, zero, 10
  sw a1, %lo(s+8)(a0)
      
  lui a0, %hi(s+80)
  addi a1, zero, 30
  sw a1, %lo(s+80)(a0)
      
  Which will save one instruction per access.


https://reviews.llvm.org/D46989

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  test/CodeGen/RISCV/byval.ll
  test/CodeGen/RISCV/double-mem.ll
  test/CodeGen/RISCV/float-mem.ll
  test/CodeGen/RISCV/fp128.ll
  test/CodeGen/RISCV/hoist-global-addr-base.ll
  test/CodeGen/RISCV/mem.ll
  test/CodeGen/RISCV/wide-mem.ll
  test/CodeGen/RISCV/zext-with-load-is-free.ll

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