[PATCH] D46179: [X86] Lowering adds/addus/subs/subus intrinsics to native IR (LLVM part)

[Tomasz Krupa via Phabricator via llvm-commits]

tkrupa added inline comments.


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Comment at: test/CodeGen/X86/avx2-intrinsics-fast-isel.ll:2585-2587
+; CHECK-NEXT:    vpmaxub %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
 ; CHECK-NEXT:    ret{{[l|q]}}
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sroland wrote:
> tkrupa wrote:
> > sroland wrote:
> > > Err, so it doesn't actually recognize the pattern?
> > Please look at my comment from Thu, May 10, 10:27 AM.
> Ah sorry I missed that.
> I'm not quite sure if that means the pattern can never be folded into a single instruction, but if so I'm very much against autoupgrade. The code might not be much worse, but in 99.99% of all cases it's going to be worse than using the intrinsic.
It only fails to fold with fast-isel (one of the non-standard instruction selection options chosen with a compiler flag); it is still always being combined with default SelectionDAGISel.


Repository:
  rL LLVM

https://reviews.llvm.org/D46179