[PATCH] D46953: [FastISel] Permit instructions to be skipped for FastISel generation.

[Simon Dardis via Phabricator via llvm-commits]

sdardis created this revision.
sdardis added a reviewer: mcrosier.
Herald added a subscriber: arichardson.

Some ISA's such as microMIPS32(https://reviews.llvm.org/source/compiler-rt/) have instructions which are near identical
for code generation purposes, e.g. xor and xor16. These instructions take the 
same value types for operands and return values, have the same
instruction predicates and map to the same ISD opcode. (These instructions do
differ by register classes.)

In such cases, the FastISel generator rejects the instruction definition.

This patch borrows the 'FastIselShouldIgnore' bit from https://reviews.llvm.org/rL129692 and enables
applying it to an instruction definition.


Repository:
  rL LLVM

https://reviews.llvm.org/D46953

Files:
  include/llvm/Target/Target.td
  utils/TableGen/CodeGenInstruction.cpp
  utils/TableGen/CodeGenInstruction.h
  utils/TableGen/FastISelEmitter.cpp


Index: utils/TableGen/FastISelEmitter.cpp
===================================================================
--- utils/TableGen/FastISelEmitter.cpp
+++ utils/TableGen/FastISelEmitter.cpp
@@ -449,10 +449,18 @@
     Record *Op = Dst->getOperator();
     if (!Op->isSubClassOf("Instruction"))
       continue;
+
     CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op);
     if (II.Operands.empty())
       continue;
 
+    // Allow instructions to be marked as unavailable for FastISel for
+    // certain cases, i.e. an ISA has two 'and' instruction which differ
+    // by what registers they can use but are otherwise identical for
+    // codegen purposes.
+    if (II.FastISelShouldIgnore)
+      continue;
+
     // For now, ignore multi-instruction patterns.
     bool MultiInsts = false;
     for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
Index: utils/TableGen/CodeGenInstruction.h
===================================================================
--- utils/TableGen/CodeGenInstruction.h
+++ utils/TableGen/CodeGenInstruction.h
@@ -258,6 +258,7 @@
     bool isInsertSubreg : 1;
     bool isConvergent : 1;
     bool hasNoSchedulingInfo : 1;
+    bool FastISelShouldIgnore : 1;
 
     std::string DeprecatedReason;
     bool HasComplexDeprecationPredicate;
Index: utils/TableGen/CodeGenInstruction.cpp
===================================================================
--- utils/TableGen/CodeGenInstruction.cpp
+++ utils/TableGen/CodeGenInstruction.cpp
@@ -327,6 +327,7 @@
   isInsertSubreg = R->getValueAsBit("isInsertSubreg");
   isConvergent = R->getValueAsBit("isConvergent");
   hasNoSchedulingInfo = R->getValueAsBit("hasNoSchedulingInfo");
+  FastISelShouldIgnore = R->getValueAsBit("FastISelShouldIgnore");
 
   bool Unset;
   mayLoad      = R->getValueAsBitOrUnset("mayLoad", Unset);
Index: include/llvm/Target/Target.td
===================================================================
--- include/llvm/Target/Target.td
+++ include/llvm/Target/Target.td
@@ -568,6 +568,12 @@
   /// can be queried via the getNamedOperandIdx() function which is generated
   /// by TableGen.
   bit UseNamedOperandTable = 0;
+
+  /// Should FastISel ignore this instruction. For certain ISAs, they have
+  /// instructions which map to the same ISD Opcode, value type operands and
+  /// instruction selection predicates. FastISel cannot handle such cases, but
+  /// SelectionDAG can.
+  bit FastISelShouldIgnore = 0;
 }
 
 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.


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