[llvm] r332446 - [mips] Add support for isBranchOffsetInRange and use it for MipsLongBranch
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Wed May 16 03:03:05 PDT 2018
Author: sdardis
Date: Wed May 16 03:03:05 2018
New Revision: 332446
URL: http://llvm.org/viewvc/llvm-project?rev=332446&view=rev
Log:
[mips] Add support for isBranchOffsetInRange and use it for MipsLongBranch
Add support for this target hook, covering MIPS, microMIPS and MIPSR6, along
with some tests. Also add missing getOppositeBranchOpc() cases exposed by the
tests.
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D46794
Added:
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int.mir
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
Modified:
llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp
llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=332446&r1=332445&r2=332446&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Wed May 16 03:03:05 2018
@@ -276,6 +276,163 @@ MipsInstrInfo::BranchType MipsInstrInfo:
return BT_CondUncond;
}
+bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const {
+ switch (BranchOpc) {
+ case Mips::B:
+ case Mips::BAL:
+ case Mips::BC1F:
+ case Mips::BC1FL:
+ case Mips::BC1T:
+ case Mips::BC1TL:
+ case Mips::BEQ: case Mips::BEQ64:
+ case Mips::BEQL:
+ case Mips::BGEZ: case Mips::BGEZ64:
+ case Mips::BGEZL:
+ case Mips::BGEZAL:
+ case Mips::BGEZALL:
+ case Mips::BGTZ: case Mips::BGTZ64:
+ case Mips::BGTZL:
+ case Mips::BLEZ: case Mips::BLEZ64:
+ case Mips::BLEZL:
+ case Mips::BLTZ: case Mips::BLTZ64:
+ case Mips::BLTZL:
+ case Mips::BLTZAL:
+ case Mips::BLTZALL:
+ case Mips::BNE: case Mips::BNE64:
+ case Mips::BNEL:
+ return isInt<18>(BrOffset);
+
+ // microMIPSr3 branches
+ case Mips::B_MM:
+ case Mips::BC1F_MM:
+ case Mips::BC1T_MM:
+ case Mips::BEQ_MM:
+ case Mips::BGEZ_MM:
+ case Mips::BGEZAL_MM:
+ case Mips::BGTZ_MM:
+ case Mips::BLEZ_MM:
+ case Mips::BLTZ_MM:
+ case Mips::BLTZAL_MM:
+ case Mips::BNE_MM:
+ case Mips::BEQZC_MM:
+ case Mips::BNEZC_MM:
+ return isInt<17>(BrOffset);
+
+ // microMIPSR3 short branches.
+ case Mips::B16_MM:
+ return isInt<11>(BrOffset);
+
+ case Mips::BEQZ16_MM:
+ case Mips::BNEZ16_MM:
+ return isInt<8>(BrOffset);
+
+ // MIPSR6 branches.
+ case Mips::BALC:
+ case Mips::BC:
+ return isInt<28>(BrOffset);
+
+ case Mips::BC1EQZ:
+ case Mips::BC1NEZ:
+ case Mips::BC2EQZ:
+ case Mips::BC2NEZ:
+ case Mips::BEQC: case Mips::BEQC64:
+ case Mips::BNEC: case Mips::BNEC64:
+ case Mips::BGEC: case Mips::BGEC64:
+ case Mips::BGEUC: case Mips::BGEUC64:
+ case Mips::BGEZC: case Mips::BGEZC64:
+ case Mips::BGTZC: case Mips::BGTZC64:
+ case Mips::BLEZC: case Mips::BLEZC64:
+ case Mips::BLTC: case Mips::BLTC64:
+ case Mips::BLTUC: case Mips::BLTUC64:
+ case Mips::BLTZC: case Mips::BLTZC64:
+ case Mips::BNVC:
+ case Mips::BOVC:
+ case Mips::BGEZALC:
+ case Mips::BEQZALC:
+ case Mips::BGTZALC:
+ case Mips::BLEZALC:
+ case Mips::BLTZALC:
+ case Mips::BNEZALC:
+ return isInt<18>(BrOffset);
+
+ case Mips::BEQZC: case Mips::BEQZC64:
+ case Mips::BNEZC: case Mips::BNEZC64:
+ return isInt<23>(BrOffset);
+
+ // microMIPSR6 branches
+ case Mips::BC16_MMR6:
+ return isInt<11>(BrOffset);
+
+ case Mips::BEQZC16_MMR6:
+ case Mips::BNEZC16_MMR6:
+ return isInt<8>(BrOffset);
+
+ case Mips::BALC_MMR6:
+ case Mips::BC_MMR6:
+ return isInt<27>(BrOffset);
+
+ case Mips::BC1EQZC_MMR6:
+ case Mips::BC1NEZC_MMR6:
+ case Mips::BC2EQZC_MMR6:
+ case Mips::BC2NEZC_MMR6:
+ case Mips::BGEZALC_MMR6:
+ case Mips::BEQZALC_MMR6:
+ case Mips::BGTZALC_MMR6:
+ case Mips::BLEZALC_MMR6:
+ case Mips::BLTZALC_MMR6:
+ case Mips::BNEZALC_MMR6:
+ case Mips::BNVC_MMR6:
+ case Mips::BOVC_MMR6:
+ return isInt<17>(BrOffset);
+
+ case Mips::BEQC_MMR6:
+ case Mips::BNEC_MMR6:
+ case Mips::BGEC_MMR6:
+ case Mips::BGEUC_MMR6:
+ case Mips::BGEZC_MMR6:
+ case Mips::BGTZC_MMR6:
+ case Mips::BLEZC_MMR6:
+ case Mips::BLTC_MMR6:
+ case Mips::BLTUC_MMR6:
+ case Mips::BLTZC_MMR6:
+ return isInt<18>(BrOffset);
+
+ case Mips::BEQZC_MMR6:
+ case Mips::BNEZC_MMR6:
+ return isInt<23>(BrOffset);
+
+ // DSP branches.
+ case Mips::BPOSGE32:
+ return isInt<18>(BrOffset);
+ case Mips::BPOSGE32_MM:
+ case Mips::BPOSGE32C_MMR3:
+ return isInt<17>(BrOffset);
+
+ // cnMIPS branches.
+ case Mips::BBIT0:
+ case Mips::BBIT032:
+ case Mips::BBIT1:
+ case Mips::BBIT132:
+ return isInt<18>(BrOffset);
+
+ // MSA branches.
+ case Mips::BZ_B:
+ case Mips::BZ_H:
+ case Mips::BZ_W:
+ case Mips::BZ_D:
+ case Mips::BZ_V:
+ case Mips::BNZ_B:
+ case Mips::BNZ_H:
+ case Mips::BNZ_W:
+ case Mips::BNZ_D:
+ case Mips::BNZ_V:
+ return isInt<18>(BrOffset);
+ }
+
+ llvm_unreachable("Unknown branch instruction!");
+}
+
+
/// Return the corresponding compact (no delay slot) form of a branch.
unsigned MipsInstrInfo::getEquivalentCompactForm(
const MachineBasicBlock::iterator I) const {
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=332446&r1=332445&r2=332446&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Wed May 16 03:03:05 2018
@@ -86,6 +86,10 @@ public:
/// Determine the opcode of a non-delay slot form for a branch if one exists.
unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const;
+ /// Determine if the branch target is in range.
+ bool isBranchOffsetInRange(unsigned BranchOpc,
+ int64_t BrOffset) const override;
+
/// Predicate to determine if an instruction can go in a forbidden slot.
bool SafeInForbiddenSlot(const MachineInstr &MI) const;
Modified: llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp?rev=332446&r1=332445&r2=332446&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp Wed May 16 03:03:05 2018
@@ -584,8 +584,7 @@ bool MipsLongBranch::runOnMachineFunctio
if (!I->Br || I->HasLongBranch)
continue;
- int ShVal = STI.inMicroMipsMode() ? 2 : 4;
- int64_t Offset = computeOffset(I->Br) / ShVal;
+ int64_t Offset = computeOffset(I->Br);
if (STI.isTargetNaCl()) {
// The offset calculation does not include sandboxing instructions
@@ -595,8 +594,9 @@ bool MipsLongBranch::runOnMachineFunctio
Offset *= 2;
}
- // Check if offset fits into 16-bit immediate field of branches.
- if (!ForceLongBranch && isInt<16>(Offset))
+ // Check if offset fits into the immediate field of the branch.
+ if (!ForceLongBranch &&
+ TII->isBranchOffsetInRange(I->Br->getOpcode(), Offset))
continue;
I->HasLongBranch = true;
Modified: llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp?rev=332446&r1=332445&r2=332446&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp Wed May 16 03:03:05 2018
@@ -427,6 +427,10 @@ unsigned MipsSEInstrInfo::getOppositeBra
case Mips::BGEZ: return Mips::BLTZ;
case Mips::BLTZ: return Mips::BGEZ;
case Mips::BLEZ: return Mips::BGTZ;
+ case Mips::BGTZ_MM: return Mips::BLEZ_MM;
+ case Mips::BGEZ_MM: return Mips::BLTZ_MM;
+ case Mips::BLTZ_MM: return Mips::BGEZ_MM;
+ case Mips::BLEZ_MM: return Mips::BGTZ_MM;
case Mips::BEQ64: return Mips::BNE64;
case Mips::BNE64: return Mips::BEQ64;
case Mips::BGTZ64: return Mips::BLEZ64;
@@ -435,24 +439,40 @@ unsigned MipsSEInstrInfo::getOppositeBra
case Mips::BLEZ64: return Mips::BGTZ64;
case Mips::BC1T: return Mips::BC1F;
case Mips::BC1F: return Mips::BC1T;
- case Mips::BEQZC_MM: return Mips::BNEZC_MM;
- case Mips::BNEZC_MM: return Mips::BEQZC_MM;
+ case Mips::BC1T_MM: return Mips::BC1F_MM;
+ case Mips::BC1F_MM: return Mips::BC1T_MM;
+ case Mips::BEQZ16_MM: return Mips::BNEZ16_MM;
+ case Mips::BNEZ16_MM: return Mips::BEQZ16_MM;
+ case Mips::BEQZC_MM: return Mips::BNEZC_MM;
+ case Mips::BNEZC_MM: return Mips::BEQZC_MM;
case Mips::BEQZC: return Mips::BNEZC;
case Mips::BNEZC: return Mips::BEQZC;
- case Mips::BEQC: return Mips::BNEC;
- case Mips::BNEC: return Mips::BEQC;
- case Mips::BGTZC: return Mips::BLEZC;
+ case Mips::BLEZC: return Mips::BGTZC;
case Mips::BGEZC: return Mips::BLTZC;
+ case Mips::BGEC: return Mips::BLTC;
+ case Mips::BGTZC: return Mips::BLEZC;
case Mips::BLTZC: return Mips::BGEZC;
- case Mips::BLEZC: return Mips::BGTZC;
+ case Mips::BLTC: return Mips::BGEC;
+ case Mips::BGEUC: return Mips::BLTUC;
+ case Mips::BLTUC: return Mips::BGEUC;
+ case Mips::BEQC: return Mips::BNEC;
+ case Mips::BNEC: return Mips::BEQC;
+ case Mips::BC1EQZ: return Mips::BC1NEZ;
+ case Mips::BC1NEZ: return Mips::BC1EQZ;
case Mips::BEQZC_MMR6: return Mips::BNEZC_MMR6;
case Mips::BNEZC_MMR6: return Mips::BEQZC_MMR6;
- case Mips::BEQC_MMR6: return Mips::BNEC_MMR6;
- case Mips::BNEC_MMR6: return Mips::BEQC_MMR6;
- case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR6;
+ case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR6;
case Mips::BGEZC_MMR6: return Mips::BLTZC_MMR6;
+ case Mips::BGEC_MMR6: return Mips::BLTC_MMR6;
+ case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR6;
case Mips::BLTZC_MMR6: return Mips::BGEZC_MMR6;
- case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR6;
+ case Mips::BLTC_MMR6: return Mips::BGEC_MMR6;
+ case Mips::BGEUC_MMR6: return Mips::BLTUC_MMR6;
+ case Mips::BLTUC_MMR6: return Mips::BGEUC_MMR6;
+ case Mips::BEQC_MMR6: return Mips::BNEC_MMR6;
+ case Mips::BNEC_MMR6: return Mips::BEQC_MMR6;
+ case Mips::BC1EQZC_MMR6: return Mips::BC1NEZC_MMR6;
+ case Mips::BC1NEZC_MMR6: return Mips::BC1EQZC_MMR6;
case Mips::BEQZC64: return Mips::BNEZC64;
case Mips::BNEZC64: return Mips::BEQZC64;
case Mips::BEQC64: return Mips::BNEC64;
@@ -469,6 +489,16 @@ unsigned MipsSEInstrInfo::getOppositeBra
case Mips::BBIT1: return Mips::BBIT0;
case Mips::BBIT032: return Mips::BBIT132;
case Mips::BBIT132: return Mips::BBIT032;
+ case Mips::BZ_B: return Mips::BNZ_B;
+ case Mips::BZ_H: return Mips::BNZ_H;
+ case Mips::BZ_W: return Mips::BNZ_W;
+ case Mips::BZ_D: return Mips::BNZ_D;
+ case Mips::BZ_V: return Mips::BNZ_V;
+ case Mips::BNZ_B: return Mips::BZ_B;
+ case Mips::BNZ_H: return Mips::BZ_H;
+ case Mips::BNZ_W: return Mips::BZ_W;
+ case Mips::BNZ_D: return Mips::BZ_D;
+ case Mips::BNZ_V: return Mips::BZ_V;
}
}
Added: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir?rev=332446&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir Wed May 16 03:03:05 2018
@@ -0,0 +1,215 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mips-mti-linux-gnu -mattr=+micromips %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch | FileCheck %s --check-prefix=MM
+# RUN: llc -mtriple=mips-mti-linux-gnu -mattr=+micromips %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch -relocation-model=pic | FileCheck %s --check-prefix=PIC
+
+# Test the long branch expansion of various branches
+
+--- |
+
+ define i32 @a(double %a, double %b) {
+ entry:
+ %cmp = fcmp une double %a, %b
+ br i1 %cmp, label %if.then, label %return
+
+ if.then:
+ call void asm sideeffect ".space 310680", "~{$1}"()
+ ret i32 0
+
+ return:
+ ret i32 1
+ }
+
+ define i32 @b(double %a, double %b) {
+ entry:
+ %cmp = fcmp ueq double %a, %b
+ br i1 %cmp, label %if.then, label %return
+
+ if.then:
+ call void asm sideeffect ".space 310680", "~{$1}"()
+ ret i32 0
+
+ return:
+ ret i32 1
+ }
+
+...
+---
+name: a
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$d6', virtual-reg: '' }
+ - { reg: '$d7', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MM-LABEL: name: a
+ ; MM: bb.0.entry:
+ ; MM: successors: %bb.2(0x50000000), %bb.1(0x30000000)
+ ; MM: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
+ ; MM: BC1F_MM $fcc0, %bb.2, implicit-def $at {
+ ; MM: NOP
+ ; MM: }
+ ; MM: bb.1.entry:
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: J %bb.3, implicit-def $at {
+ ; MM: NOP
+ ; MM: }
+ ; MM: bb.2.if.then:
+ ; MM: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; MM: $v0 = LI16_MM 0
+ ; MM: JRC16_MM undef $ra, implicit killed $v0
+ ; MM: bb.3.return:
+ ; MM: $v0 = LI16_MM 1
+ ; MM: JRC16_MM undef $ra, implicit killed $v0
+ ; PIC-LABEL: name: a
+ ; PIC: bb.0.entry:
+ ; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
+ ; PIC: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
+ ; PIC: BC1F_MM $fcc0, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1.entry:
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2.entry:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: JR $at {
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: }
+ ; PIC: bb.3.if.then:
+ ; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: $v0 = LI16_MM 0
+ ; PIC: JRC16_MM undef $ra, implicit killed $v0
+ ; PIC: bb.4.return:
+ ; PIC: $v0 = LI16_MM 1
+ ; PIC: JRC16_MM undef $ra, implicit killed $v0
+ bb.0.entry:
+ successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ liveins: $d6, $d7
+
+ FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
+ BC1T_MM killed $fcc0, %bb.2, implicit-def dead $at
+
+ bb.1.if.then:
+ INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ $v0 = LI16_MM 0
+ PseudoReturn undef $ra, implicit killed $v0
+
+ bb.2.return:
+ $v0 = LI16_MM 1
+ PseudoReturn undef $ra, implicit killed $v0
+
+...
+---
+name: b
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$d6', virtual-reg: '' }
+ - { reg: '$d7', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MM-LABEL: name: b
+ ; MM: bb.0.entry:
+ ; MM: successors: %bb.2(0x30000000), %bb.1(0x50000000)
+ ; MM: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
+ ; MM: BC1F_MM killed $fcc0, %bb.1, implicit-def dead $at {
+ ; MM: NOP
+ ; MM: }
+ ; MM: bb.1.return:
+ ; MM: $v0 = LI16_MM 1
+ ; MM: JRC16_MM undef $ra, implicit killed $v0
+ ; MM: bb.2.if.then:
+ ; MM: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; MM: $v0 = LI16_MM 0
+ ; MM: JRC16_MM undef $ra, implicit killed $v0
+ ; PIC-LABEL: name: b
+ ; PIC: bb.0.entry:
+ ; PIC: successors: %bb.2(0x30000000), %bb.1(0x50000000)
+ ; PIC: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
+ ; PIC: BC1F_MM killed $fcc0, %bb.1, implicit-def dead $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1.return:
+ ; PIC: $v0 = LI16_MM 1
+ ; PIC: JRC16_MM undef $ra, implicit killed $v0
+ ; PIC: bb.2.if.then:
+ ; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: $v0 = LI16_MM 0
+ ; PIC: JRC16_MM undef $ra, implicit killed $v0
+ bb.0.entry:
+ successors: %bb.1(0x30000000), %bb.2(0x50000000)
+ liveins: $d6, $d7
+
+ FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
+ BC1F_MM killed $fcc0, %bb.2, implicit-def dead $at
+
+ bb.2.return:
+ $v0 = LI16_MM 1
+ PseudoReturn undef $ra, implicit killed $v0
+
+ bb.1.if.then:
+ INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ $v0 = LI16_MM 0
+ PseudoReturn undef $ra, implicit killed $v0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir?rev=332446&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir Wed May 16 03:03:05 2018
@@ -0,0 +1,219 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch | FileCheck %s --check-prefix=MM
+# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch -relocation-model=pic | FileCheck %s --check-prefix=PIC
+
+# Test the long branch expansion of various branches
+
+--- |
+
+ define i32 @a(double %a, double %b) {
+ entry:
+ %cmp = fcmp une double %a, %b
+ br i1 %cmp, label %if.then, label %return
+
+ if.then:
+ call void asm sideeffect ".space 810680", "~{$1}"()
+ ret i32 0
+
+ return:
+ ret i32 1
+ }
+
+ define i32 @b(double %a, double %b) {
+ entry:
+ %cmp = fcmp ueq double %a, %b
+ br i1 %cmp, label %if.then, label %return
+
+ if.then:
+ call void asm sideeffect ".space 810680", "~{$1}"()
+ ret i32 0
+
+ return:
+ ret i32 1
+ }
+
+...
+---
+name: a
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$d12_64', virtual-reg: '' }
+ - { reg: '$d14_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MM-LABEL: name: a
+ ; MM: bb.0.entry:
+ ; MM: successors: %bb.2(0x50000000), %bb.1(0x30000000)
+ ; MM: $f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64
+ ; MM: BC1EQZC_MMR6 $d0_64, %bb.2, implicit-def $at
+ ; MM: bb.1.entry:
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: BC_MMR6 %bb.3
+ ; MM: bb.2.if.then:
+ ; MM: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MM: $v0 = LI16_MM 0
+ ; MM: JRC16_MM undef $ra, implicit $v0
+ ; MM: bb.3.return:
+ ; MM: $v0 = LI16_MM 1
+ ; MM: JRC16_MM undef $ra, implicit $v0
+ ; PIC-LABEL: name: a
+ ; PIC: bb.0.entry:
+ ; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
+ ; PIC: $f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64
+ ; PIC: BC1EQZC_MMR6 $d0_64, %bb.3, implicit-def $at
+ ; PIC: bb.1.entry:
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: bb.2.entry:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: bb.3.if.then:
+ ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: $v0 = LI16_MM 0
+ ; PIC: JRC16_MM undef $ra, implicit $v0
+ ; PIC: bb.4.return:
+ ; PIC: $v0 = LI16_MM 1
+ ; PIC: JRC16_MM undef $ra, implicit $v0
+ bb.0.entry:
+ successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ liveins: $d12_64, $d14_64
+
+ $f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64
+ BC1NEZC_MMR6 killed $d0_64, %bb.2, implicit-def $at
+
+ bb.1.if.then:
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ $v0 = LI16_MM 0
+ PseudoReturn undef $ra, implicit $v0
+
+ bb.2.return:
+ $v0 = LI16_MM 1
+ PseudoReturn undef $ra, implicit $v0
+
+...
+---
+name: b
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$d12_64', virtual-reg: '' }
+ - { reg: '$d14_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MM-LABEL: name: b
+ ; MM: bb.0.entry:
+ ; MM: successors: %bb.2(0x30000000), %bb.1(0x50000000)
+ ; MM: $f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64
+ ; MM: BC1NEZC_MMR6 $d0_64, %bb.2, implicit-def $at
+ ; MM: bb.1.entry:
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: BC_MMR6 %bb.3
+ ; MM: bb.2.if.then:
+ ; MM: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MM: $v0 = LI16_MM 0
+ ; MM: JRC16_MM undef $ra, implicit $v0
+ ; MM: bb.3.return:
+ ; MM: $v0 = LI16_MM 1
+ ; MM: JRC16_MM undef $ra, implicit $v0
+ ; PIC-LABEL: name: b
+ ; PIC: bb.0.entry:
+ ; PIC: successors: %bb.3(0x30000000), %bb.1(0x50000000)
+ ; PIC: $f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64
+ ; PIC: BC1NEZC_MMR6 $d0_64, %bb.3, implicit-def $at
+ ; PIC: bb.1.entry:
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: bb.2.entry:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: bb.3.if.then:
+ ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: $v0 = LI16_MM 0
+ ; PIC: JRC16_MM undef $ra, implicit $v0
+ ; PIC: bb.4.return:
+ ; PIC: $v0 = LI16_MM 1
+ ; PIC: JRC16_MM undef $ra, implicit $v0
+ bb.0.entry:
+ successors: %bb.1(0x30000000), %bb.2(0x50000000)
+ liveins: $d12_64, $d14_64
+
+ $f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64
+ BC1EQZC_MMR6 killed $d0_64, %bb.2, implicit-def $at
+
+ bb.1.if.then:
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ $v0 = LI16_MM 0
+ PseudoReturn undef $ra, implicit $v0
+
+ bb.2.return:
+ $v0 = LI16_MM 1
+ PseudoReturn undef $ra, implicit $v0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir?rev=332446&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir Wed May 16 03:03:05 2018
@@ -0,0 +1,242 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mips-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch | FileCheck %s --check-prefix=MIPS
+# RUN: llc -mtriple=mips-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch -relocation-model=pic | FileCheck %s --check-prefix=PIC
+# Test the long branch expansion of various branches
+
+--- |
+
+ define i32 @a(double %a, double %b) {
+ entry:
+ %cmp = fcmp une double %a, %b
+ br i1 %cmp, label %if.then, label %return
+
+ if.then:
+ call void asm sideeffect ".space 310680", "~{$1}"()
+ ret i32 0
+
+ return:
+ ret i32 1
+ }
+
+ define i32 @b(double %a, double %b) {
+ entry:
+ %cmp = fcmp une double %a, %b
+ br i1 %cmp, label %if.then, label %return
+
+ if.then:
+ call void asm sideeffect ".space 310680", "~{$1}"()
+ ret i32 0
+
+ return:
+ ret i32 1
+ }
+
+...
+---
+name: a
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$d6', virtual-reg: '' }
+ - { reg: '$d7', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS-LABEL: name: a
+ ; MIPS: bb.0.entry:
+ ; MIPS: successors: %bb.2(0x50000000), %bb.1(0x30000000)
+ ; MIPS: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
+ ; MIPS: BC1F $fcc0, %bb.2, implicit-def $at {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; MIPS: bb.1.entry:
+ ; MIPS: successors: %bb.3(0x80000000)
+ ; MIPS: J %bb.3, implicit-def $at {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; MIPS: bb.2.if.then:
+ ; MIPS: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; MIPS: PseudoReturn undef $ra, implicit killed $v0 {
+ ; MIPS: $v0 = ADDiu $zero, 0
+ ; MIPS: }
+ ; MIPS: bb.3.return:
+ ; MIPS: PseudoReturn undef $ra, implicit killed $v0 {
+ ; MIPS: $v0 = ADDiu $zero, 1
+ ; MIPS: }
+ ; PIC-LABEL: name: a
+ ; PIC: bb.0.entry:
+ ; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
+ ; PIC: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
+ ; PIC: BC1F $fcc0, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1.entry:
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2.entry:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: JR $at {
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: }
+ ; PIC: bb.3.if.then:
+ ; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: PseudoReturn undef $ra, implicit killed $v0 {
+ ; PIC: $v0 = ADDiu $zero, 0
+ ; PIC: }
+ ; PIC: bb.4.return:
+ ; PIC: PseudoReturn undef $ra, implicit killed $v0 {
+ ; PIC: $v0 = ADDiu $zero, 1
+ ; PIC: }
+ bb.0.entry:
+ successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ liveins: $d6, $d7
+
+ FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
+ BC1T killed $fcc0, %bb.2, implicit-def $at
+
+ bb.1.if.then:
+ INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ $v0 = ADDiu $zero, 0
+ PseudoReturn undef $ra, implicit killed $v0
+
+ bb.2.return:
+ $v0 = ADDiu $zero, 1
+ PseudoReturn undef $ra, implicit killed $v0
+
+...
+---
+name: b
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$d6', virtual-reg: '' }
+ - { reg: '$d7', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS-LABEL: name: b
+ ; MIPS: bb.0.entry:
+ ; MIPS: successors: %bb.2(0x50000000), %bb.1(0x30000000)
+ ; MIPS: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
+ ; MIPS: BC1T $fcc0, %bb.2, implicit-def $at {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; MIPS: bb.1.entry:
+ ; MIPS: successors: %bb.3(0x80000000)
+ ; MIPS: J %bb.3, implicit-def $at {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; MIPS: bb.2.if.then:
+ ; MIPS: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; MIPS: PseudoReturn undef $ra, implicit killed $v0 {
+ ; MIPS: $v0 = ADDiu $zero, 0
+ ; MIPS: }
+ ; MIPS: bb.3.return:
+ ; MIPS: PseudoReturn undef $ra, implicit killed $v0 {
+ ; MIPS: $v0 = ADDiu $zero, 1
+ ; MIPS: }
+ ; PIC-LABEL: name: b
+ ; PIC: bb.0.entry:
+ ; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
+ ; PIC: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
+ ; PIC: BC1T $fcc0, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1.entry:
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2.entry:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: JR $at {
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: }
+ ; PIC: bb.3.if.then:
+ ; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: PseudoReturn undef $ra, implicit killed $v0 {
+ ; PIC: $v0 = ADDiu $zero, 0
+ ; PIC: }
+ ; PIC: bb.4.return:
+ ; PIC: PseudoReturn undef $ra, implicit killed $v0 {
+ ; PIC: $v0 = ADDiu $zero, 1
+ ; PIC: }
+ bb.0.entry:
+ successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ liveins: $d6, $d7
+
+ FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
+ BC1F killed $fcc0, %bb.2, implicit-def $at
+
+ bb.1.if.then:
+ INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ $v0 = ADDiu $zero, 0
+ PseudoReturn undef $ra, implicit killed $v0
+
+ bb.2.return:
+ $v0 = ADDiu $zero, 1
+ PseudoReturn undef $ra, implicit killed $v0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir?rev=332446&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir Wed May 16 03:03:05 2018
@@ -0,0 +1,236 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch | FileCheck %s --check-prefix=R6
+# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch -relocation-model=pic | FileCheck %s --check-prefix=PIC
+
+# Test the long branch expansion of various branches
+
+--- |
+
+ define i32 @a(double %a, double %b) {
+ entry:
+ %cmp = fcmp une double %a, %b
+ br i1 %cmp, label %if.then, label %return
+
+ if.then: ; preds = %entry
+ call void asm sideeffect ".space 310680", "~{$1}"()
+ ret i32 0
+
+ return: ; preds = %entry
+ ret i32 1
+ }
+
+ define i32 @b(double %a, double %b) {
+ entry:
+ %cmp = fcmp ueq double %a, %b
+ br i1 %cmp, label %if.then, label %return
+
+ if.then: ; preds = %entry
+ call void asm sideeffect ".space 310680", "~{$1}"()
+ ret i32 0
+
+ return: ; preds = %entry
+ ret i32 1
+ }
+
+
+...
+---
+name: a
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$d12_64', virtual-reg: '' }
+ - { reg: '$d14_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; R6-LABEL: name: a
+ ; R6: bb.0.entry:
+ ; R6: successors: %bb.2(0x50000000), %bb.1(0x30000000)
+ ; R6: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
+ ; R6: BC1NEZ $d0_64, %bb.2 {
+ ; R6: NOP
+ ; R6: }
+ ; R6: bb.1.entry:
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: BC %bb.3
+ ; R6: bb.2.if.then:
+ ; R6: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; R6: PseudoReturn undef $ra, implicit killed $v0 {
+ ; R6: $v0 = ADDiu $zero, 0
+ ; R6: }
+ ; R6: bb.3.return:
+ ; R6: PseudoReturn undef $ra, implicit killed $v0 {
+ ; R6: $v0 = ADDiu $zero, 1
+ ; R6: }
+ ; PIC-LABEL: name: a
+ ; PIC: bb.0.entry:
+ ; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
+ ; PIC: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
+ ; PIC: BC1NEZ $d0_64, %bb.3 {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1.entry:
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: bb.2.entry:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: bb.3.if.then:
+ ; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: PseudoReturn undef $ra, implicit killed $v0 {
+ ; PIC: $v0 = ADDiu $zero, 0
+ ; PIC: }
+ ; PIC: bb.4.return:
+ ; PIC: PseudoReturn undef $ra, implicit killed $v0 {
+ ; PIC: $v0 = ADDiu $zero, 1
+ ; PIC: }
+ bb.0.entry:
+ successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ liveins: $d12_64, $d14_64
+
+ $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
+ BC1EQZ killed $d0_64, %bb.2, implicit-def $at
+
+ bb.1.if.then:
+ INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ $v0 = ADDiu $zero, 0
+ PseudoReturn undef $ra, implicit killed $v0
+
+ bb.2.return:
+ $v0 = ADDiu $zero, 1
+ PseudoReturn undef $ra, implicit killed $v0
+
+...
+---
+name: b
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$d12_64', virtual-reg: '' }
+ - { reg: '$d14_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; R6-LABEL: name: b
+ ; R6: bb.0.entry:
+ ; R6: successors: %bb.2(0x50000000), %bb.1(0x30000000)
+ ; R6: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
+ ; R6: BC1EQZ $d0_64, %bb.2 {
+ ; R6: NOP
+ ; R6: }
+ ; R6: bb.1.entry:
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: BC %bb.3
+ ; R6: bb.2.if.then:
+ ; R6: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; R6: PseudoReturn undef $ra, implicit killed $v0 {
+ ; R6: $v0 = ADDiu $zero, 0
+ ; R6: }
+ ; R6: bb.3.return:
+ ; R6: PseudoReturn undef $ra, implicit killed $v0 {
+ ; R6: $v0 = ADDiu $zero, 1
+ ; R6: }
+ ; PIC-LABEL: name: b
+ ; PIC: bb.0.entry:
+ ; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
+ ; PIC: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
+ ; PIC: BC1EQZ $d0_64, %bb.3 {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1.entry:
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: bb.2.entry:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: bb.3.if.then:
+ ; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: PseudoReturn undef $ra, implicit killed $v0 {
+ ; PIC: $v0 = ADDiu $zero, 0
+ ; PIC: }
+ ; PIC: bb.4.return:
+ ; PIC: PseudoReturn undef $ra, implicit killed $v0 {
+ ; PIC: $v0 = ADDiu $zero, 1
+ ; PIC: }
+ bb.0.entry:
+ successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ liveins: $d12_64, $d14_64
+
+ $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
+ BC1NEZ killed $d0_64, %bb.2, implicit-def $at
+
+ bb.1.if.then:
+ INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ $v0 = ADDiu $zero, 0
+ PseudoReturn undef $ra, implicit killed $v0
+
+ bb.2.return:
+ $v0 = ADDiu $zero, 1
+ PseudoReturn undef $ra, implicit killed $v0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir?rev=332446&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir Wed May 16 03:03:05 2018
@@ -0,0 +1,848 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mips-mti-linux-gnu -mattr=+micromips -o - %s -start-before mips-delay-slot-filler -stop-after mips-long-branch | FileCheck %s --check-prefix=MM
+# RUN: llc -mtriple=mips-mti-linux-gnu -mattr=+micromips -o - %s -start-before mips-delay-slot-filler -stop-after mips-long-branch -relocation-model=pic | FileCheck %s --check-prefix=PIC
+
+# Test the long branch expansion of various branches
+
+--- |
+ define void @expand_BEQ_MM(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BGEZ_MM(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BGTZ_MM(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BLEZ_MM(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BLTZ_MM(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BNE_MM(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BEQZ16_MM(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BNEZ16_MM(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+...
+---
+
+name: expand_BEQ_MM
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MM-LABEL: name: expand_BEQ_MM
+ ; MM: bb.0 (%ir-block.0):
+ ; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MM: renamable $at = ANDi killed renamable $a0, 1
+ ; MM: BNEZC_MM $at, %bb.2, implicit-def $at
+ ; MM: bb.1 (%ir-block.0):
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: J %bb.3, implicit-def $at {
+ ; MM: NOP
+ ; MM: }
+ ; MM: bb.2.iftrue:
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: INLINEASM &".space 131068", 1
+ ; MM: bb.3.tail:
+ ; MM: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BEQ_MM
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BNEZC_MM $at, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: JR $at {
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BEQ_MM killed renamable $at, $zero, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BGEZ_MM
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MM-LABEL: name: expand_BGEZ_MM
+ ; MM: bb.0 (%ir-block.0):
+ ; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MM: renamable $at = ANDi killed renamable $a0, 1
+ ; MM: BLTZ_MM $at, %bb.2, implicit-def $at {
+ ; MM: NOP
+ ; MM: }
+ ; MM: bb.1 (%ir-block.0):
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: J %bb.3, implicit-def $at {
+ ; MM: NOP
+ ; MM: }
+ ; MM: bb.2.iftrue:
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: INLINEASM &".space 131068", 1
+ ; MM: bb.3.tail:
+ ; MM: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BGEZ_MM
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BLTZ_MM $at, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: JR $at {
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BGEZ_MM killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BGTZ_MM
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MM-LABEL: name: expand_BGTZ_MM
+ ; MM: bb.0 (%ir-block.0):
+ ; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MM: renamable $at = ANDi killed renamable $a0, 1
+ ; MM: BLEZ_MM $at, %bb.2, implicit-def $at {
+ ; MM: NOP
+ ; MM: }
+ ; MM: bb.1 (%ir-block.0):
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: J %bb.3, implicit-def $at {
+ ; MM: NOP
+ ; MM: }
+ ; MM: bb.2.iftrue:
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: INLINEASM &".space 131068", 1
+ ; MM: bb.3.tail:
+ ; MM: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BGTZ_MM
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BLEZ_MM $at, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: JR $at {
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BGTZ_MM killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BLEZ_MM
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MM-LABEL: name: expand_BLEZ_MM
+ ; MM: bb.0 (%ir-block.0):
+ ; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MM: renamable $at = ANDi killed renamable $a0, 1
+ ; MM: BGTZ_MM $at, %bb.2, implicit-def $at {
+ ; MM: NOP
+ ; MM: }
+ ; MM: bb.1 (%ir-block.0):
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: J %bb.3, implicit-def $at {
+ ; MM: NOP
+ ; MM: }
+ ; MM: bb.2.iftrue:
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: INLINEASM &".space 131068", 1
+ ; MM: bb.3.tail:
+ ; MM: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BLEZ_MM
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BGTZ_MM $at, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: JR $at {
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BLEZ_MM killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BLTZ_MM
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MM-LABEL: name: expand_BLTZ_MM
+ ; MM: bb.0 (%ir-block.0):
+ ; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MM: renamable $at = ANDi killed renamable $a0, 1
+ ; MM: BGEZ_MM $at, %bb.2, implicit-def $at {
+ ; MM: NOP
+ ; MM: }
+ ; MM: bb.1 (%ir-block.0):
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: J %bb.3, implicit-def $at {
+ ; MM: NOP
+ ; MM: }
+ ; MM: bb.2.iftrue:
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: INLINEASM &".space 131068", 1
+ ; MM: bb.3.tail:
+ ; MM: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BLTZ_MM
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BGEZ_MM $at, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: JR $at {
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BLTZ_MM killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BNE_MM
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MM-LABEL: name: expand_BNE_MM
+ ; MM: bb.0 (%ir-block.0):
+ ; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MM: renamable $at = ANDi killed renamable $a0, 1
+ ; MM: BEQZC_MM $at, %bb.2, implicit-def $at
+ ; MM: bb.1 (%ir-block.0):
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: J %bb.3, implicit-def $at {
+ ; MM: NOP
+ ; MM: }
+ ; MM: bb.2.iftrue:
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: INLINEASM &".space 131068", 1
+ ; MM: bb.3.tail:
+ ; MM: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BNE_MM
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BEQZC_MM $at, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: JR $at {
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BNE_MM killed renamable $at, $zero, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BEQZ16_MM
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MM-LABEL: name: expand_BEQZ16_MM
+ ; MM: bb.0 (%ir-block.0):
+ ; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MM: renamable $v0 = ANDi killed renamable $a0, 1
+ ; MM: BNEZ16_MM $v0, %bb.2, implicit-def $at {
+ ; MM: NOP
+ ; MM: }
+ ; MM: bb.1 (%ir-block.0):
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: J %bb.3, implicit-def $at {
+ ; MM: NOP
+ ; MM: }
+ ; MM: bb.2.iftrue:
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: INLINEASM &".space 131068", 1
+ ; MM: bb.3.tail:
+ ; MM: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BEQZ16_MM
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $v0 = ANDi killed renamable $a0, 1
+ ; PIC: BNEZ16_MM $v0, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: JR $at {
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $v0 = ANDi killed renamable $a0, 1
+ BEQZ16_MM killed renamable $v0, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BNEZ16_MM
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MM-LABEL: name: expand_BNEZ16_MM
+ ; MM: bb.0 (%ir-block.0):
+ ; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MM: renamable $v0 = ANDi killed renamable $a0, 1
+ ; MM: BEQZ16_MM $v0, %bb.2, implicit-def $at {
+ ; MM: NOP
+ ; MM: }
+ ; MM: bb.1 (%ir-block.0):
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: J %bb.3, implicit-def $at {
+ ; MM: NOP
+ ; MM: }
+ ; MM: bb.2.iftrue:
+ ; MM: successors: %bb.3(0x80000000)
+ ; MM: INLINEASM &".space 131068", 1
+ ; MM: bb.3.tail:
+ ; MM: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BNEZ16_MM
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $v0 = ANDi killed renamable $a0, 1
+ ; PIC: BEQZ16_MM $v0, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: JR $at {
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $v0 = ANDi killed renamable $a0, 1
+ BNEZ16_MM killed renamable $v0, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
Added: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir?rev=332446&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir Wed May 16 03:03:05 2018
@@ -0,0 +1,1184 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips -o - %s -start-before mips-delay-slot-filler -stop-after mips-long-branch | FileCheck %s --check-prefix=MMR6
+# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips -o - %s -start-before mips-delay-slot-filler -stop-after mips-long-branch -relocation-model=pic | FileCheck %s --check-prefix=PIC
+
+# Test the long branch expansion of various branches
+
+--- |
+ define void @expand_BEQC_MMR6(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BNEC_MMR6(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BGEC_MMR6(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BGEUC_MMR6(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BGEZC_MMR6(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BGTZC_MMR6(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BLEZC_MMR6(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BLTC_MMR6(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BLTUC_MMR6(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BLTZC_MMR6(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BEQZC_MMR6(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 8388608", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BNEZC_MMR6(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 8388608", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+...
+---
+
+name: expand_BEQC_MMR6
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MMR6-LABEL: name: expand_BEQC_MMR6
+ ; MMR6: bb.0 (%ir-block.0):
+ ; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MMR6: renamable $at = ANDi killed renamable $a0, 1
+ ; MMR6: BNEC_MMR6 $at, $zero, %bb.2, implicit-def $at
+ ; MMR6: bb.1 (%ir-block.0):
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: BC_MMR6 %bb.3
+ ; MMR6: bb.2.iftrue:
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: INLINEASM &".space 131068", 1
+ ; MMR6: bb.3.tail:
+ ; MMR6: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BEQC_MMR6
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BNEC_MMR6 $at, $zero, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BEQC_MMR6 killed renamable $at, $zero, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BNEC_MMR6
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MMR6-LABEL: name: expand_BNEC_MMR6
+ ; MMR6: bb.0 (%ir-block.0):
+ ; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MMR6: renamable $at = ANDi killed renamable $a0, 1
+ ; MMR6: BEQC_MMR6 $at, $zero, %bb.2, implicit-def $at
+ ; MMR6: bb.1 (%ir-block.0):
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: BC_MMR6 %bb.3
+ ; MMR6: bb.2.iftrue:
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: INLINEASM &".space 131068", 1
+ ; MMR6: bb.3.tail:
+ ; MMR6: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BNEC_MMR6
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BEQC_MMR6 $at, $zero, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BNEC_MMR6 killed renamable $at, $zero, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BGEC_MMR6
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MMR6-LABEL: name: expand_BGEC_MMR6
+ ; MMR6: bb.0 (%ir-block.0):
+ ; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MMR6: renamable $at = ANDi killed renamable $a0, 1
+ ; MMR6: BLTC_MMR6 $at, $zero, %bb.2, implicit-def $at
+ ; MMR6: bb.1 (%ir-block.0):
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: BC_MMR6 %bb.3
+ ; MMR6: bb.2.iftrue:
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: INLINEASM &".space 131068", 1
+ ; MMR6: bb.3.tail:
+ ; MMR6: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BGEC_MMR6
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BLTC_MMR6 $at, $zero, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BGEC_MMR6 killed renamable $at, $zero, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BGEUC_MMR6
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MMR6-LABEL: name: expand_BGEUC_MMR6
+ ; MMR6: bb.0 (%ir-block.0):
+ ; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MMR6: renamable $at = ANDi killed renamable $a0, 1
+ ; MMR6: BLTUC_MMR6 $at, $zero, %bb.2, implicit-def $at
+ ; MMR6: bb.1 (%ir-block.0):
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: BC_MMR6 %bb.3
+ ; MMR6: bb.2.iftrue:
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: INLINEASM &".space 131068", 1
+ ; MMR6: bb.3.tail:
+ ; MMR6: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BGEUC_MMR6
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BLTUC_MMR6 $at, $zero, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BGEUC_MMR6 killed renamable $at, $zero, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BGEZC_MMR6
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MMR6-LABEL: name: expand_BGEZC_MMR6
+ ; MMR6: bb.0 (%ir-block.0):
+ ; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MMR6: renamable $at = ANDi killed renamable $a0, 1
+ ; MMR6: BLTZC_MMR6 $at, %bb.2, implicit-def $at
+ ; MMR6: bb.1 (%ir-block.0):
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: BC_MMR6 %bb.3
+ ; MMR6: bb.2.iftrue:
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: INLINEASM &".space 131068", 1
+ ; MMR6: bb.3.tail:
+ ; MMR6: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BGEZC_MMR6
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BLTZC_MMR6 $at, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BGEZC_MMR6 killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BGTZC_MMR6
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MMR6-LABEL: name: expand_BGTZC_MMR6
+ ; MMR6: bb.0 (%ir-block.0):
+ ; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MMR6: renamable $at = ANDi killed renamable $a0, 1
+ ; MMR6: BLEZC_MMR6 $at, %bb.2, implicit-def $at
+ ; MMR6: bb.1 (%ir-block.0):
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: BC_MMR6 %bb.3
+ ; MMR6: bb.2.iftrue:
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: INLINEASM &".space 131068", 1
+ ; MMR6: bb.3.tail:
+ ; MMR6: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BGTZC_MMR6
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BLEZC_MMR6 $at, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BGTZC_MMR6 killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BLEZC_MMR6
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MMR6-LABEL: name: expand_BLEZC_MMR6
+ ; MMR6: bb.0 (%ir-block.0):
+ ; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MMR6: renamable $at = ANDi killed renamable $a0, 1
+ ; MMR6: BGTZC_MMR6 $at, %bb.2, implicit-def $at
+ ; MMR6: bb.1 (%ir-block.0):
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: BC_MMR6 %bb.3
+ ; MMR6: bb.2.iftrue:
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: INLINEASM &".space 131068", 1
+ ; MMR6: bb.3.tail:
+ ; MMR6: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BLEZC_MMR6
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BGTZC_MMR6 $at, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BLEZC_MMR6 killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BLTC_MMR6
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MMR6-LABEL: name: expand_BLTC_MMR6
+ ; MMR6: bb.0 (%ir-block.0):
+ ; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MMR6: renamable $at = ANDi killed renamable $a0, 1
+ ; MMR6: BGEC_MMR6 $at, $zero, %bb.2, implicit-def $at
+ ; MMR6: bb.1 (%ir-block.0):
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: BC_MMR6 %bb.3
+ ; MMR6: bb.2.iftrue:
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: INLINEASM &".space 131068", 1
+ ; MMR6: bb.3.tail:
+ ; MMR6: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BLTC_MMR6
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BGEC_MMR6 $at, $zero, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BLTC_MMR6 killed renamable $at, $zero, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BLTUC_MMR6
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MMR6-LABEL: name: expand_BLTUC_MMR6
+ ; MMR6: bb.0 (%ir-block.0):
+ ; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MMR6: renamable $at = ANDi killed renamable $a0, 1
+ ; MMR6: BGEUC_MMR6 $at, $zero, %bb.2, implicit-def $at
+ ; MMR6: bb.1 (%ir-block.0):
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: BC_MMR6 %bb.3
+ ; MMR6: bb.2.iftrue:
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: INLINEASM &".space 131068", 1
+ ; MMR6: bb.3.tail:
+ ; MMR6: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BLTUC_MMR6
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BGEUC_MMR6 $at, $zero, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BLTUC_MMR6 killed renamable $at, $zero, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BLTZC_MMR6
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MMR6-LABEL: name: expand_BLTZC_MMR6
+ ; MMR6: bb.0 (%ir-block.0):
+ ; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MMR6: renamable $at = ANDi killed renamable $a0, 1
+ ; MMR6: BGEZC_MMR6 $at, %bb.2, implicit-def $at
+ ; MMR6: bb.1 (%ir-block.0):
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: BC_MMR6 %bb.3
+ ; MMR6: bb.2.iftrue:
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: INLINEASM &".space 131068", 1
+ ; MMR6: bb.3.tail:
+ ; MMR6: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BLTZC_MMR6
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BGEZC_MMR6 $at, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BLTZC_MMR6 killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BEQZC_MMR6
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MMR6-LABEL: name: expand_BEQZC_MMR6
+ ; MMR6: bb.0 (%ir-block.0):
+ ; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MMR6: renamable $at = ANDi killed renamable $a0, 1
+ ; MMR6: BNEZC_MMR6 $at, %bb.2, implicit-def $at
+ ; MMR6: bb.1 (%ir-block.0):
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: BC_MMR6 %bb.3
+ ; MMR6: bb.2.iftrue:
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: INLINEASM &".space 8388608", 1
+ ; MMR6: bb.3.tail:
+ ; MMR6: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BEQZC_MMR6
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BNEZC_MMR6 $at, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 8388608", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BEQZC_MMR6 killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 8388608", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BNEZC_MMR6
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MMR6-LABEL: name: expand_BNEZC_MMR6
+ ; MMR6: bb.0 (%ir-block.0):
+ ; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MMR6: renamable $at = ANDi killed renamable $a0, 1
+ ; MMR6: BEQZC_MMR6 $at, %bb.2, implicit-def $at
+ ; MMR6: bb.1 (%ir-block.0):
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: BC_MMR6 %bb.3
+ ; MMR6: bb.2.iftrue:
+ ; MMR6: successors: %bb.3(0x80000000)
+ ; MMR6: INLINEASM &".space 8388608", 1
+ ; MMR6: bb.3.tail:
+ ; MMR6: JRC16_MM undef $ra
+ ; PIC-LABEL: name: expand_BNEZC_MMR6
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BEQZC_MMR6 $at, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 8388608", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JRC16_MM undef $ra
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BNEZC_MMR6 killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 8388608", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
Added: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir?rev=332446&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir Wed May 16 03:03:05 2018
@@ -0,0 +1,692 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mips64-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch | FileCheck %s --check-prefix=MIPS64
+# RUN: llc -mtriple=mips64-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch -relocation-model=pic | FileCheck %s --check-prefix=PIC
+
+# Test the long branch expansion of various branches
+
+--- |
+ define i64 @expand_BEQ64(i64 %a, i64 %b) {
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ ret i64 1
+
+ tail:
+ ret i64 0
+ }
+
+ define i64 @expand_BNE64(i64 %a, i64 %b) {
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ ret i64 1
+
+ tail:
+ ret i64 0
+ }
+
+ define i64 @expand_BGEZ64(i64 %a, i64 %b) {
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ ret i64 1
+
+ tail:
+ ret i64 0
+ }
+
+ define i64 @expand_BGTZ64(i64 %a, i64 %b) {
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ ret i64 1
+
+ tail:
+ ret i64 0
+ }
+
+ define i64 @expand_BLEZ64(i64 %a, i64 %b) {
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ ret i64 1
+
+ tail:
+ ret i64 0
+ }
+
+ define i64 @expand_BLTZ64(i64 %a, i64 %b) {
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ ret i64 1
+
+ tail:
+ ret i64 0
+ }
+
+...
+---
+
+name: expand_BEQ64
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS64-LABEL: name: expand_BEQ64
+ ; MIPS64: bb.0 (%ir-block.0):
+ ; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS64: BNE64 $a0_64, $zero_64, %bb.2, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.1 (%ir-block.0):
+ ; MIPS64: successors: %bb.3(0x80000000)
+ ; MIPS64: J %bb.3, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.2.iftrue:
+ ; MIPS64: INLINEASM &".space 131068", 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: }
+ ; MIPS64: bb.3.tail:
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: }
+ ; PIC-LABEL: name: expand_BEQ64
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: BNE64 $a0_64, $zero_64, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: }
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64
+
+ BEQ64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ INLINEASM &".space 131068", 1
+ $v0_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+ bb.2.tail:
+ $v0_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+...
+---
+
+name: expand_BNE64
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS64-LABEL: name: expand_BNE64
+ ; MIPS64: bb.0 (%ir-block.0):
+ ; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS64: BEQ64 $a0_64, $zero_64, %bb.2, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.1 (%ir-block.0):
+ ; MIPS64: successors: %bb.3(0x80000000)
+ ; MIPS64: J %bb.3, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.2.iftrue:
+ ; MIPS64: INLINEASM &".space 131068", 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: }
+ ; MIPS64: bb.3.tail:
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: }
+ ; PIC-LABEL: name: expand_BNE64
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: BEQ64 $a0_64, $zero_64, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: }
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64
+
+ BNE64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ INLINEASM &".space 131068", 1
+ $v0_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+ bb.2.tail:
+ $v0_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+...
+---
+
+name: expand_BGEZ64
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS64-LABEL: name: expand_BGEZ64
+ ; MIPS64: bb.0 (%ir-block.0):
+ ; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS64: BLTZ64 $a0_64, %bb.2, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.1 (%ir-block.0):
+ ; MIPS64: successors: %bb.3(0x80000000)
+ ; MIPS64: J %bb.3, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.2.iftrue:
+ ; MIPS64: INLINEASM &".space 131068", 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: }
+ ; MIPS64: bb.3.tail:
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: }
+ ; PIC-LABEL: name: expand_BGEZ64
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: BLTZ64 $a0_64, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: }
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64
+
+ BGEZ64 killed renamable $a0_64, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ INLINEASM &".space 131068", 1
+ $v0_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+ bb.2.tail:
+ $v0_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+...
+---
+
+name: expand_BGTZ64
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS64-LABEL: name: expand_BGTZ64
+ ; MIPS64: bb.0 (%ir-block.0):
+ ; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS64: BLEZ64 $a0_64, %bb.2, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.1 (%ir-block.0):
+ ; MIPS64: successors: %bb.3(0x80000000)
+ ; MIPS64: J %bb.3, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.2.iftrue:
+ ; MIPS64: INLINEASM &".space 131068", 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: }
+ ; MIPS64: bb.3.tail:
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: }
+ ; PIC-LABEL: name: expand_BGTZ64
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: BLEZ64 $a0_64, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: }
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64
+
+ BGTZ64 killed renamable $a0_64, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ INLINEASM &".space 131068", 1
+ $v0_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+ bb.2.tail:
+ $v0_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+...
+---
+
+name: expand_BLEZ64
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS64-LABEL: name: expand_BLEZ64
+ ; MIPS64: bb.0 (%ir-block.0):
+ ; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS64: BGTZ64 $a0_64, %bb.2, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.1 (%ir-block.0):
+ ; MIPS64: successors: %bb.3(0x80000000)
+ ; MIPS64: J %bb.3, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.2.iftrue:
+ ; MIPS64: INLINEASM &".space 131068", 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: }
+ ; MIPS64: bb.3.tail:
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: }
+ ; PIC-LABEL: name: expand_BLEZ64
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: BGTZ64 $a0_64, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: }
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64
+
+ BLEZ64 killed renamable $a0_64, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ INLINEASM &".space 131068", 1
+ $v0_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+ bb.2.tail:
+ $v0_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+...
+---
+
+name: expand_BLTZ64
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS64-LABEL: name: expand_BLTZ64
+ ; MIPS64: bb.0 (%ir-block.0):
+ ; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS64: BGEZ64 $a0_64, %bb.2, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.1 (%ir-block.0):
+ ; MIPS64: successors: %bb.3(0x80000000)
+ ; MIPS64: J %bb.3, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.2.iftrue:
+ ; MIPS64: INLINEASM &".space 131068", 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: }
+ ; MIPS64: bb.3.tail:
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: }
+ ; PIC-LABEL: name: expand_BLTZ64
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: BGEZ64 $a0_64, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: }
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64
+
+ BLTZ64 killed renamable $a0_64, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ INLINEASM &".space 131068", 1
+ $v0_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+ bb.2.tail:
+ $v0_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir?rev=332446&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir Wed May 16 03:03:05 2018
@@ -0,0 +1,1286 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mips64-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch | FileCheck %s --check-prefix=MIPS64
+# RUN: llc -mtriple=mips64-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch -relocation-model=pic | FileCheck %s --check-prefix=PIC
+
+# Test the long branch expansion of various branches
+
+--- |
+ define i64 @expand_BNEZC64(i64 %a, i64 %b) {
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 831068", ""()
+ ret i64 1
+
+ tail:
+ ret i64 0
+ }
+
+ define i64 @expand_BEQZC64(i64 %a, i64 %b) {
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 831068", ""()
+ ret i64 1
+
+ tail:
+ ret i64 0
+ }
+
+ define i64 @expand_BNEC64(i64 %a, i64 %b) {
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 831068", ""()
+ ret i64 1
+
+ tail:
+ ret i64 0
+ }
+
+ define i64 @expand_BEQC64(i64 %a, i64 %b) {
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 831068", ""()
+ ret i64 1
+
+ tail:
+ ret i64 0
+ }
+
+ define i64 @expand_BLTC64(i64 %a, i64 %b) {
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 831068", ""()
+ ret i64 1
+
+ tail:
+ ret i64 0
+ }
+
+ define i64 @expand_BLTUC64(i64 %a, i64 %b) {
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 831068", ""()
+ ret i64 1
+
+ tail:
+ ret i64 0
+ }
+
+ define i64 @expand_BGEC64(i64 %a, i64 %b) {
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 831068", ""()
+ ret i64 1
+
+ tail:
+ ret i64 0
+ }
+
+ define i64 @expand_BGEUC64(i64 %a, i64 %b) {
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 831068", ""()
+ ret i64 1
+
+ tail:
+ ret i64 0
+ }
+
+ define i64 @expand_BLEZC64(i64 %a, i64 %b) {
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 831068", ""()
+ ret i64 1
+
+ tail:
+ ret i64 0
+ }
+
+ define i64 @expand_BLTZC64(i64 %a, i64 %b) {
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 831068", ""()
+ ret i64 1
+
+ tail:
+ ret i64 0
+ }
+
+ define i64 @expand_BGEZC64(i64 %a, i64 %b) {
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 831068", ""()
+ ret i64 1
+
+ tail:
+ ret i64 0
+ }
+
+ define i64 @expand_BGTZC64(i64 %a, i64 %b) {
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 831068", ""()
+ ret i64 1
+
+ tail:
+ ret i64 0
+ }
+
+...
+---
+
+name: expand_BNEZC64
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS64-LABEL: name: expand_BNEZC64
+ ; MIPS64: bb.0 (%ir-block.0):
+ ; MIPS64: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; MIPS64: BNEZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+ ; MIPS64: bb.1.iftrue:
+ ; MIPS64: INLINEASM &".space 831068", 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: }
+ ; MIPS64: bb.2.tail:
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: }
+ ; PIC-LABEL: name: expand_BNEZC64
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; PIC: BNEZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+ ; PIC: bb.1.iftrue:
+ ; PIC: INLINEASM &".space 831068", 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: }
+ ; PIC: bb.2.tail:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64
+
+ BNEZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ INLINEASM &".space 831068", 1
+ $v0_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+ bb.2.tail:
+ $v0_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+...
+---
+
+name: expand_BEQZC64
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS64-LABEL: name: expand_BEQZC64
+ ; MIPS64: bb.0 (%ir-block.0):
+ ; MIPS64: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; MIPS64: BEQZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+ ; MIPS64: bb.1.iftrue:
+ ; MIPS64: INLINEASM &".space 831068", 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: }
+ ; MIPS64: bb.2.tail:
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: }
+ ; PIC-LABEL: name: expand_BEQZC64
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; PIC: BEQZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+ ; PIC: bb.1.iftrue:
+ ; PIC: INLINEASM &".space 831068", 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: }
+ ; PIC: bb.2.tail:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64
+
+ BEQZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ INLINEASM &".space 831068", 1
+ $v0_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+ bb.2.tail:
+ $v0_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+...
+---
+
+name: expand_BNEC64
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS64-LABEL: name: expand_BNEC64
+ ; MIPS64: bb.0 (%ir-block.0):
+ ; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS64: BEQC64 $a0_64, $zero_64, %bb.2, implicit-def $at
+ ; MIPS64: bb.1 (%ir-block.0):
+ ; MIPS64: successors: %bb.3(0x80000000)
+ ; MIPS64: J %bb.3, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.2.iftrue:
+ ; MIPS64: INLINEASM &".space 831068", 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: }
+ ; MIPS64: bb.3.tail:
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: }
+ ; PIC-LABEL: name: expand_BNEC64
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: BEQC64 $a0_64, $zero_64, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: INLINEASM &".space 831068", 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: }
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64
+
+ BNEC64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ INLINEASM &".space 831068", 1
+ $v0_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+ bb.2.tail:
+ $v0_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+...
+---
+
+name: expand_BEQC64
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS64-LABEL: name: expand_BEQC64
+ ; MIPS64: bb.0 (%ir-block.0):
+ ; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS64: BNEC64 $a0_64, $zero_64, %bb.2, implicit-def $at
+ ; MIPS64: bb.1 (%ir-block.0):
+ ; MIPS64: successors: %bb.3(0x80000000)
+ ; MIPS64: J %bb.3, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.2.iftrue:
+ ; MIPS64: INLINEASM &".space 831068", 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: }
+ ; MIPS64: bb.3.tail:
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: }
+ ; PIC-LABEL: name: expand_BEQC64
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: BNEC64 $a0_64, $zero_64, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: INLINEASM &".space 831068", 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: }
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64
+
+ BEQC64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ INLINEASM &".space 831068", 1
+ $v0_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+ bb.2.tail:
+ $v0_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+...
+---
+
+name: expand_BLTC64
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS64-LABEL: name: expand_BLTC64
+ ; MIPS64: bb.0 (%ir-block.0):
+ ; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS64: BGEC64 $a0_64, $zero_64, %bb.2, implicit-def $at
+ ; MIPS64: bb.1 (%ir-block.0):
+ ; MIPS64: successors: %bb.3(0x80000000)
+ ; MIPS64: J %bb.3, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.2.iftrue:
+ ; MIPS64: INLINEASM &".space 831068", 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: }
+ ; MIPS64: bb.3.tail:
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: }
+ ; PIC-LABEL: name: expand_BLTC64
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: BGEC64 $a0_64, $zero_64, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: INLINEASM &".space 831068", 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: }
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64
+
+ BLTC64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ INLINEASM &".space 831068", 1
+ $v0_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+ bb.2.tail:
+ $v0_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+...
+---
+
+name: expand_BLTUC64
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS64-LABEL: name: expand_BLTUC64
+ ; MIPS64: bb.0 (%ir-block.0):
+ ; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS64: BGEUC64 $a0_64, $zero_64, %bb.2, implicit-def $at
+ ; MIPS64: bb.1 (%ir-block.0):
+ ; MIPS64: successors: %bb.3(0x80000000)
+ ; MIPS64: J %bb.3, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.2.iftrue:
+ ; MIPS64: INLINEASM &".space 831068", 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: }
+ ; MIPS64: bb.3.tail:
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: }
+ ; PIC-LABEL: name: expand_BLTUC64
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: BGEUC64 $a0_64, $zero_64, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: INLINEASM &".space 831068", 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: }
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64
+
+ BLTUC64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ INLINEASM &".space 831068", 1
+ $v0_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+ bb.2.tail:
+ $v0_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+...
+---
+
+name: expand_BGEC64
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS64-LABEL: name: expand_BGEC64
+ ; MIPS64: bb.0 (%ir-block.0):
+ ; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS64: BLTC64 $a0_64, $zero_64, %bb.2, implicit-def $at
+ ; MIPS64: bb.1 (%ir-block.0):
+ ; MIPS64: successors: %bb.3(0x80000000)
+ ; MIPS64: J %bb.3, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.2.iftrue:
+ ; MIPS64: INLINEASM &".space 831068", 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: }
+ ; MIPS64: bb.3.tail:
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: }
+ ; PIC-LABEL: name: expand_BGEC64
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: BLTC64 $a0_64, $zero_64, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: INLINEASM &".space 831068", 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: }
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64
+
+ BGEC64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ INLINEASM &".space 831068", 1
+ $v0_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+ bb.2.tail:
+ $v0_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+...
+---
+
+name: expand_BGEUC64
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS64-LABEL: name: expand_BGEUC64
+ ; MIPS64: bb.0 (%ir-block.0):
+ ; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS64: BLTUC64 $a0_64, $zero_64, %bb.2, implicit-def $at
+ ; MIPS64: bb.1 (%ir-block.0):
+ ; MIPS64: successors: %bb.3(0x80000000)
+ ; MIPS64: J %bb.3, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.2.iftrue:
+ ; MIPS64: INLINEASM &".space 831068", 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: }
+ ; MIPS64: bb.3.tail:
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: }
+ ; PIC-LABEL: name: expand_BGEUC64
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: BLTUC64 $a0_64, $zero_64, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: INLINEASM &".space 831068", 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: }
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64
+
+ BGEUC64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ INLINEASM &".space 831068", 1
+ $v0_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+ bb.2.tail:
+ $v0_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+...
+---
+
+name: expand_BLEZC64
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS64-LABEL: name: expand_BLEZC64
+ ; MIPS64: bb.0 (%ir-block.0):
+ ; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS64: BGTZC64 $a0_64, %bb.2, implicit-def $at
+ ; MIPS64: bb.1 (%ir-block.0):
+ ; MIPS64: successors: %bb.3(0x80000000)
+ ; MIPS64: J %bb.3, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.2.iftrue:
+ ; MIPS64: INLINEASM &".space 831068", 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: }
+ ; MIPS64: bb.3.tail:
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: }
+ ; PIC-LABEL: name: expand_BLEZC64
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: BGTZC64 $a0_64, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: INLINEASM &".space 831068", 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: }
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64
+
+ BLEZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ INLINEASM &".space 831068", 1
+ $v0_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+ bb.2.tail:
+ $v0_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+...
+---
+
+name: expand_BLTZC64
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS64-LABEL: name: expand_BLTZC64
+ ; MIPS64: bb.0 (%ir-block.0):
+ ; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS64: BGEZC64 $a0_64, %bb.2, implicit-def $at
+ ; MIPS64: bb.1 (%ir-block.0):
+ ; MIPS64: successors: %bb.3(0x80000000)
+ ; MIPS64: J %bb.3, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.2.iftrue:
+ ; MIPS64: INLINEASM &".space 831068", 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: }
+ ; MIPS64: bb.3.tail:
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: }
+ ; PIC-LABEL: name: expand_BLTZC64
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: BGEZC64 $a0_64, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: INLINEASM &".space 831068", 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: }
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64
+
+ BLTZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ INLINEASM &".space 831068", 1
+ $v0_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+ bb.2.tail:
+ $v0_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+...
+---
+
+name: expand_BGEZC64
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS64-LABEL: name: expand_BGEZC64
+ ; MIPS64: bb.0 (%ir-block.0):
+ ; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS64: BLTZC64 $a0_64, %bb.2, implicit-def $at
+ ; MIPS64: bb.1 (%ir-block.0):
+ ; MIPS64: successors: %bb.3(0x80000000)
+ ; MIPS64: J %bb.3, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.2.iftrue:
+ ; MIPS64: INLINEASM &".space 831068", 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: }
+ ; MIPS64: bb.3.tail:
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: }
+ ; PIC-LABEL: name: expand_BGEZC64
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: BLTZC64 $a0_64, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: INLINEASM &".space 831068", 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: }
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64
+
+ BGEZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ INLINEASM &".space 831068", 1
+ $v0_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+ bb.2.tail:
+ $v0_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+...
+---
+
+name: expand_BGTZC64
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS64-LABEL: name: expand_BGTZC64
+ ; MIPS64: bb.0 (%ir-block.0):
+ ; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS64: BLEZC64 $a0_64, %bb.2, implicit-def $at
+ ; MIPS64: bb.1 (%ir-block.0):
+ ; MIPS64: successors: %bb.3(0x80000000)
+ ; MIPS64: J %bb.3, implicit-def $at {
+ ; MIPS64: NOP
+ ; MIPS64: }
+ ; MIPS64: bb.2.iftrue:
+ ; MIPS64: INLINEASM &".space 831068", 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: }
+ ; MIPS64: bb.3.tail:
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: }
+ ; PIC-LABEL: name: expand_BGTZC64
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: BLEZC64 $a0_64, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: INLINEASM &".space 831068", 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: }
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64
+
+ BGTZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ INLINEASM &".space 831068", 1
+ $v0_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+ bb.2.tail:
+ $v0_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir?rev=332446&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir Wed May 16 03:03:05 2018
@@ -0,0 +1,1184 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -o - %s -start-before mips-delay-slot-filler -stop-after mips-long-branch | FileCheck %s --check-prefix=R6
+# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -o - %s -start-before mips-delay-slot-filler -stop-after mips-long-branch -relocation-model=pic | FileCheck %s --check-prefix=PIC
+
+# Test the long branch expansion of various branches
+
+--- |
+ define void @expand_BEQC(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BNEC(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BGEC(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BGEUC(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BGEZC(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BGTZC(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BLEZC(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BLTC(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BLTUC(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BLTZC(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BEQZC(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 8388608", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BNEZC(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 8388608", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+...
+---
+
+name: expand_BEQC
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; R6-LABEL: name: expand_BEQC
+ ; R6: bb.0 (%ir-block.0):
+ ; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; R6: renamable $at = ANDi killed renamable $a0, 1
+ ; R6: BNEC $at, $zero, %bb.2, implicit-def $at
+ ; R6: bb.1 (%ir-block.0):
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: BC %bb.3
+ ; R6: bb.2.iftrue:
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: INLINEASM &".space 131068", 1
+ ; R6: bb.3.tail:
+ ; R6: JIC undef $ra, 0, implicit-def $at
+ ; PIC-LABEL: name: expand_BEQC
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BNEC $at, $zero, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JIC undef $ra, 0, implicit-def $at
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BEQC killed renamable $at, $zero, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BNEC
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; R6-LABEL: name: expand_BNEC
+ ; R6: bb.0 (%ir-block.0):
+ ; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; R6: renamable $at = ANDi killed renamable $a0, 1
+ ; R6: BEQC $at, $zero, %bb.2, implicit-def $at
+ ; R6: bb.1 (%ir-block.0):
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: BC %bb.3
+ ; R6: bb.2.iftrue:
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: INLINEASM &".space 131068", 1
+ ; R6: bb.3.tail:
+ ; R6: JIC undef $ra, 0, implicit-def $at
+ ; PIC-LABEL: name: expand_BNEC
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BEQC $at, $zero, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JIC undef $ra, 0, implicit-def $at
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BNEC killed renamable $at, $zero, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BGEC
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; R6-LABEL: name: expand_BGEC
+ ; R6: bb.0 (%ir-block.0):
+ ; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; R6: renamable $at = ANDi killed renamable $a0, 1
+ ; R6: BLTC $at, $zero, %bb.2, implicit-def $at
+ ; R6: bb.1 (%ir-block.0):
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: BC %bb.3
+ ; R6: bb.2.iftrue:
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: INLINEASM &".space 131068", 1
+ ; R6: bb.3.tail:
+ ; R6: JIC undef $ra, 0, implicit-def $at
+ ; PIC-LABEL: name: expand_BGEC
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BLTC $at, $zero, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JIC undef $ra, 0, implicit-def $at
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BGEC killed renamable $at, $zero, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BGEUC
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; R6-LABEL: name: expand_BGEUC
+ ; R6: bb.0 (%ir-block.0):
+ ; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; R6: renamable $at = ANDi killed renamable $a0, 1
+ ; R6: BLTUC $at, $zero, %bb.2, implicit-def $at
+ ; R6: bb.1 (%ir-block.0):
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: BC %bb.3
+ ; R6: bb.2.iftrue:
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: INLINEASM &".space 131068", 1
+ ; R6: bb.3.tail:
+ ; R6: JIC undef $ra, 0, implicit-def $at
+ ; PIC-LABEL: name: expand_BGEUC
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BLTUC $at, $zero, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JIC undef $ra, 0, implicit-def $at
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BGEUC killed renamable $at, $zero, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BGEZC
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; R6-LABEL: name: expand_BGEZC
+ ; R6: bb.0 (%ir-block.0):
+ ; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; R6: renamable $at = ANDi killed renamable $a0, 1
+ ; R6: BLTZC $at, %bb.2, implicit-def $at
+ ; R6: bb.1 (%ir-block.0):
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: BC %bb.3
+ ; R6: bb.2.iftrue:
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: INLINEASM &".space 131068", 1
+ ; R6: bb.3.tail:
+ ; R6: JIC undef $ra, 0, implicit-def $at
+ ; PIC-LABEL: name: expand_BGEZC
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BLTZC $at, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JIC undef $ra, 0, implicit-def $at
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BGEZC killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BGTZC
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; R6-LABEL: name: expand_BGTZC
+ ; R6: bb.0 (%ir-block.0):
+ ; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; R6: renamable $at = ANDi killed renamable $a0, 1
+ ; R6: BLEZC $at, %bb.2, implicit-def $at
+ ; R6: bb.1 (%ir-block.0):
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: BC %bb.3
+ ; R6: bb.2.iftrue:
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: INLINEASM &".space 131068", 1
+ ; R6: bb.3.tail:
+ ; R6: JIC undef $ra, 0, implicit-def $at
+ ; PIC-LABEL: name: expand_BGTZC
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BLEZC $at, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JIC undef $ra, 0, implicit-def $at
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BGTZC killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BLEZC
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; R6-LABEL: name: expand_BLEZC
+ ; R6: bb.0 (%ir-block.0):
+ ; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; R6: renamable $at = ANDi killed renamable $a0, 1
+ ; R6: BGTZC $at, %bb.2, implicit-def $at
+ ; R6: bb.1 (%ir-block.0):
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: BC %bb.3
+ ; R6: bb.2.iftrue:
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: INLINEASM &".space 131068", 1
+ ; R6: bb.3.tail:
+ ; R6: JIC undef $ra, 0, implicit-def $at
+ ; PIC-LABEL: name: expand_BLEZC
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BGTZC $at, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JIC undef $ra, 0, implicit-def $at
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BLEZC killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BLTC
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; R6-LABEL: name: expand_BLTC
+ ; R6: bb.0 (%ir-block.0):
+ ; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; R6: renamable $at = ANDi killed renamable $a0, 1
+ ; R6: BGEC $at, $zero, %bb.2, implicit-def $at
+ ; R6: bb.1 (%ir-block.0):
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: BC %bb.3
+ ; R6: bb.2.iftrue:
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: INLINEASM &".space 131068", 1
+ ; R6: bb.3.tail:
+ ; R6: JIC undef $ra, 0, implicit-def $at
+ ; PIC-LABEL: name: expand_BLTC
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BGEC $at, $zero, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JIC undef $ra, 0, implicit-def $at
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BLTC killed renamable $at, $zero, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BLTUC
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; R6-LABEL: name: expand_BLTUC
+ ; R6: bb.0 (%ir-block.0):
+ ; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; R6: renamable $at = ANDi killed renamable $a0, 1
+ ; R6: BGEUC $at, $zero, %bb.2, implicit-def $at
+ ; R6: bb.1 (%ir-block.0):
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: BC %bb.3
+ ; R6: bb.2.iftrue:
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: INLINEASM &".space 131068", 1
+ ; R6: bb.3.tail:
+ ; R6: JIC undef $ra, 0, implicit-def $at
+ ; PIC-LABEL: name: expand_BLTUC
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BGEUC $at, $zero, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JIC undef $ra, 0, implicit-def $at
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BLTUC killed renamable $at, $zero, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BLTZC
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; R6-LABEL: name: expand_BLTZC
+ ; R6: bb.0 (%ir-block.0):
+ ; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; R6: renamable $at = ANDi killed renamable $a0, 1
+ ; R6: BGEZC $at, %bb.2, implicit-def $at
+ ; R6: bb.1 (%ir-block.0):
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: BC %bb.3
+ ; R6: bb.2.iftrue:
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: INLINEASM &".space 131068", 1
+ ; R6: bb.3.tail:
+ ; R6: JIC undef $ra, 0, implicit-def $at
+ ; PIC-LABEL: name: expand_BLTZC
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BGEZC $at, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JIC undef $ra, 0, implicit-def $at
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BLTZC killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BEQZC
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; R6-LABEL: name: expand_BEQZC
+ ; R6: bb.0 (%ir-block.0):
+ ; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; R6: renamable $at = ANDi killed renamable $a0, 1
+ ; R6: BNEZC $at, %bb.2, implicit-def $at
+ ; R6: bb.1 (%ir-block.0):
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: BC %bb.3
+ ; R6: bb.2.iftrue:
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: INLINEASM &".space 8388608", 1
+ ; R6: bb.3.tail:
+ ; R6: JIC undef $ra, 0, implicit-def $at
+ ; PIC-LABEL: name: expand_BEQZC
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BNEZC $at, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 8388608", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JIC undef $ra, 0, implicit-def $at
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BEQZC killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 8388608", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BNEZC
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; R6-LABEL: name: expand_BNEZC
+ ; R6: bb.0 (%ir-block.0):
+ ; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; R6: renamable $at = ANDi killed renamable $a0, 1
+ ; R6: BEQZC $at, %bb.2, implicit-def $at
+ ; R6: bb.1 (%ir-block.0):
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: BC %bb.3
+ ; R6: bb.2.iftrue:
+ ; R6: successors: %bb.3(0x80000000)
+ ; R6: INLINEASM &".space 8388608", 1
+ ; R6: bb.3.tail:
+ ; R6: JIC undef $ra, 0, implicit-def $at
+ ; PIC-LABEL: name: expand_BNEZC
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BEQZC $at, %bb.3, implicit-def $at
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 8388608", 1
+ ; PIC: bb.4.tail:
+ ; PIC: JIC undef $ra, 0, implicit-def $at
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BNEZC killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 8388608", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
Added: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int.mir?rev=332446&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int.mir Wed May 16 03:03:05 2018
@@ -0,0 +1,668 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mips-mti-linux-gnu -o - %s -start-before mips-delay-slot-filler -stop-after mips-long-branch | FileCheck %s --check-prefix=MIPS
+# RUN: llc -mtriple=mips-mti-linux-gnu -o - %s -start-before mips-delay-slot-filler -stop-after mips-long-branch -relocation-model=pic | FileCheck %s --check-prefix=PIC
+
+# Test the long branch expansion of various branches
+
+--- |
+ define void @expand_BEQ(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BGEZ(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BGTZ(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BLEZ(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BLTZ(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+ define void @expand_BNE(i1 %a) {
+ br i1 %a, label %iftrue, label %tail
+
+ iftrue:
+ call void asm sideeffect ".space 131068", ""()
+ br label %tail
+
+ tail:
+ ret void
+ }
+
+...
+---
+
+name: expand_BEQ
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS-LABEL: name: expand_BEQ
+ ; MIPS: bb.0 (%ir-block.0):
+ ; MIPS: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS: renamable $at = ANDi killed renamable $a0, 1
+ ; MIPS: BNE $at, $zero, %bb.2, implicit-def $at {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; MIPS: bb.1 (%ir-block.0):
+ ; MIPS: successors: %bb.3(0x80000000)
+ ; MIPS: J %bb.3, implicit-def $at {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; MIPS: bb.2.iftrue:
+ ; MIPS: successors: %bb.3(0x80000000)
+ ; MIPS: INLINEASM &".space 131068", 1
+ ; MIPS: bb.3.tail:
+ ; MIPS: PseudoReturn undef $ra {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; PIC-LABEL: name: expand_BEQ
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BNE $at, $zero, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: JR $at {
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn undef $ra {
+ ; PIC: NOP
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BEQ killed renamable $at, $zero, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BGEZ
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS-LABEL: name: expand_BGEZ
+ ; MIPS: bb.0 (%ir-block.0):
+ ; MIPS: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS: renamable $at = ANDi killed renamable $a0, 1
+ ; MIPS: BLTZ $at, %bb.2, implicit-def $at {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; MIPS: bb.1 (%ir-block.0):
+ ; MIPS: successors: %bb.3(0x80000000)
+ ; MIPS: J %bb.3, implicit-def $at {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; MIPS: bb.2.iftrue:
+ ; MIPS: successors: %bb.3(0x80000000)
+ ; MIPS: INLINEASM &".space 131068", 1
+ ; MIPS: bb.3.tail:
+ ; MIPS: PseudoReturn undef $ra {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; PIC-LABEL: name: expand_BGEZ
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BLTZ $at, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: JR $at {
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn undef $ra {
+ ; PIC: NOP
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BGEZ killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BGTZ
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS-LABEL: name: expand_BGTZ
+ ; MIPS: bb.0 (%ir-block.0):
+ ; MIPS: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS: renamable $at = ANDi killed renamable $a0, 1
+ ; MIPS: BLEZ $at, %bb.2, implicit-def $at {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; MIPS: bb.1 (%ir-block.0):
+ ; MIPS: successors: %bb.3(0x80000000)
+ ; MIPS: J %bb.3, implicit-def $at {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; MIPS: bb.2.iftrue:
+ ; MIPS: successors: %bb.3(0x80000000)
+ ; MIPS: INLINEASM &".space 131068", 1
+ ; MIPS: bb.3.tail:
+ ; MIPS: PseudoReturn undef $ra {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; PIC-LABEL: name: expand_BGTZ
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BLEZ $at, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: JR $at {
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn undef $ra {
+ ; PIC: NOP
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BGTZ killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BLEZ
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS-LABEL: name: expand_BLEZ
+ ; MIPS: bb.0 (%ir-block.0):
+ ; MIPS: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS: renamable $at = ANDi killed renamable $a0, 1
+ ; MIPS: BGTZ $at, %bb.2, implicit-def $at {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; MIPS: bb.1 (%ir-block.0):
+ ; MIPS: successors: %bb.3(0x80000000)
+ ; MIPS: J %bb.3, implicit-def $at {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; MIPS: bb.2.iftrue:
+ ; MIPS: successors: %bb.3(0x80000000)
+ ; MIPS: INLINEASM &".space 131068", 1
+ ; MIPS: bb.3.tail:
+ ; MIPS: PseudoReturn undef $ra {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; PIC-LABEL: name: expand_BLEZ
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BGTZ $at, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: JR $at {
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn undef $ra {
+ ; PIC: NOP
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BLEZ killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BLTZ
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS-LABEL: name: expand_BLTZ
+ ; MIPS: bb.0 (%ir-block.0):
+ ; MIPS: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS: renamable $at = ANDi killed renamable $a0, 1
+ ; MIPS: BGEZ $at, %bb.2, implicit-def $at {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; MIPS: bb.1 (%ir-block.0):
+ ; MIPS: successors: %bb.3(0x80000000)
+ ; MIPS: J %bb.3, implicit-def $at {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; MIPS: bb.2.iftrue:
+ ; MIPS: successors: %bb.3(0x80000000)
+ ; MIPS: INLINEASM &".space 131068", 1
+ ; MIPS: bb.3.tail:
+ ; MIPS: PseudoReturn undef $ra {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; PIC-LABEL: name: expand_BLTZ
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BGEZ $at, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: JR $at {
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn undef $ra {
+ ; PIC: NOP
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BLTZ killed renamable $at, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
+---
+
+name: expand_BNE
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MIPS-LABEL: name: expand_BNE
+ ; MIPS: bb.0 (%ir-block.0):
+ ; MIPS: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MIPS: renamable $at = ANDi killed renamable $a0, 1
+ ; MIPS: BEQ $at, $zero, %bb.2, implicit-def $at {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; MIPS: bb.1 (%ir-block.0):
+ ; MIPS: successors: %bb.3(0x80000000)
+ ; MIPS: J %bb.3, implicit-def $at {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; MIPS: bb.2.iftrue:
+ ; MIPS: successors: %bb.3(0x80000000)
+ ; MIPS: INLINEASM &".space 131068", 1
+ ; MIPS: bb.3.tail:
+ ; MIPS: PseudoReturn undef $ra {
+ ; MIPS: NOP
+ ; MIPS: }
+ ; PIC-LABEL: name: expand_BNE
+ ; PIC: bb.0 (%ir-block.0):
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $at = ANDi killed renamable $a0, 1
+ ; PIC: BEQ $at, $zero, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1 (%ir-block.0):
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp = ADDiu $sp, -8
+ ; PIC: SW $ra, $sp, 0
+ ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2 (%ir-block.0):
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at = ADDu $ra, $at
+ ; PIC: $ra = LW $sp, 0
+ ; PIC: JR $at {
+ ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: }
+ ; PIC: bb.3.iftrue:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: INLINEASM &".space 131068", 1
+ ; PIC: bb.4.tail:
+ ; PIC: PseudoReturn undef $ra {
+ ; PIC: NOP
+ ; PIC: }
+ bb.0 (%ir-block.0):
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0
+
+ renamable $at = ANDi killed renamable $a0, 1
+ BNE killed renamable $at, $zero, %bb.2, implicit-def $at
+
+ bb.1.iftrue:
+ successors: %bb.2(0x80000000)
+
+ INLINEASM &".space 131068", 1
+
+ bb.2.tail:
+ PseudoReturn undef $ra
+
+...
Added: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-msa.mir?rev=332446&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-msa.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-msa.mir Wed May 16 03:03:05 2018
@@ -0,0 +1,1355 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips64r5 -mattr=+fp64,+msa %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch | FileCheck %s --check-prefix=MSA
+# RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips64r5 -mattr=+fp64,+msa %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch -relocation-model=pic | FileCheck %s --check-prefix=PIC
+
+# Test the long branch expansion of various branches
+
+
+
+--- |
+
+ define i32 @_Z4bz_8Dv16_a(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
+ entry:
+ %0 = bitcast i64 %d.coerce0 to <8 x i8>
+ %d.0.vec.expand = shufflevector <8 x i8> %0, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+ %1 = bitcast i64 %d.coerce1 to <8 x i8>
+ %d.8.vec.expand = shufflevector <8 x i8> %1, <8 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %d.8.vecblend = shufflevector <16 x i8> %d.8.vec.expand, <16 x i8> %d.0.vec.expand, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %2 = tail call i32 @llvm.mips.bz.b(<16 x i8> %d.8.vecblend)
+ %tobool = icmp eq i32 %2, 0
+ br i1 %tobool, label %return, label %if.then
+
+ if.then:
+ tail call void asm sideeffect ".space 810680", "~{$1}"()
+ br label %return
+
+ return:
+ %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
+ ret i32 %retval.0
+ }
+
+ declare i32 @llvm.mips.bz.b(<16 x i8>)
+
+ define i32 @_Z5bz_16Dv8_s(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
+ entry:
+ %0 = bitcast i64 %d.coerce0 to <4 x i16>
+ %d.0.vec.expand = shufflevector <4 x i16> %0, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
+ %1 = bitcast i64 %d.coerce1 to <4 x i16>
+ %d.8.vec.expand = shufflevector <4 x i16> %1, <4 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3>
+ %d.8.vecblend = shufflevector <8 x i16> %d.8.vec.expand, <8 x i16> %d.0.vec.expand, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
+ %2 = tail call i32 @llvm.mips.bz.h(<8 x i16> %d.8.vecblend)
+ %tobool = icmp eq i32 %2, 0
+ br i1 %tobool, label %return, label %if.then
+
+ if.then:
+ tail call void asm sideeffect ".space 810680", "~{$1}"()
+ br label %return
+
+ return:
+ %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
+ ret i32 %retval.0
+ }
+
+ declare i32 @llvm.mips.bz.h(<8 x i16>)
+
+ define i32 @_Z5bz_32Dv4_i(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
+ entry:
+ %0 = bitcast i64 %d.coerce0 to <2 x i32>
+ %d.0.vec.expand = shufflevector <2 x i32> %0, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+ %1 = bitcast i64 %d.coerce1 to <2 x i32>
+ %d.8.vec.expand = shufflevector <2 x i32> %1, <2 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
+ %d.8.vecblend = shufflevector <4 x i32> %d.8.vec.expand, <4 x i32> %d.0.vec.expand, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+ %2 = tail call i32 @llvm.mips.bz.w(<4 x i32> %d.8.vecblend)
+ %tobool = icmp eq i32 %2, 0
+ br i1 %tobool, label %return, label %if.then
+
+ if.then:
+ tail call void asm sideeffect ".space 810680", "~{$1}"()
+ br label %return
+
+ return:
+ %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
+ ret i32 %retval.0
+ }
+
+ declare i32 @llvm.mips.bz.w(<4 x i32>)
+
+ define i32 @_Z5bz_64Dv2_x(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
+ entry:
+ %d.0.vec.insert = insertelement <2 x i64> undef, i64 %d.coerce0, i32 0
+ %d.8.vec.insert = insertelement <2 x i64> %d.0.vec.insert, i64 %d.coerce1, i32 1
+ %0 = tail call i32 @llvm.mips.bz.d(<2 x i64> %d.8.vec.insert)
+ %tobool = icmp eq i32 %0, 0
+ br i1 %tobool, label %return, label %if.then
+
+ if.then:
+ tail call void asm sideeffect ".space 810680", "~{$1}"()
+ br label %return
+
+ return:
+ %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
+ ret i32 %retval.0
+ }
+
+ declare i32 @llvm.mips.bz.d(<2 x i64>)
+
+ define i32 @_Z5bz_64_vDv2_x(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
+ entry:
+ %d.0.vec.insert = insertelement <2 x i64> undef, i64 %d.coerce0, i32 0
+ %d.8.vec.insert = insertelement <2 x i64> %d.0.vec.insert, i64 %d.coerce1, i32 1
+ %d.16.vec.insert = bitcast <2 x i64> %d.8.vec.insert to <16 x i8>
+ %0 = tail call i32 @llvm.mips.bz.v(<16 x i8> %d.16.vec.insert)
+ %tobool = icmp eq i32 %0, 0
+ br i1 %tobool, label %return, label %if.then
+
+ if.then:
+ tail call void asm sideeffect ".space 810680", "~{$1}"()
+ br label %return
+
+ return:
+ %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
+ ret i32 %retval.0
+ }
+
+ declare i32 @llvm.mips.bz.v(<16 x i8>)
+
+ define i32 @_Z5bnz_8Dv16_a(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
+ entry:
+ %0 = bitcast i64 %d.coerce0 to <8 x i8>
+ %d.0.vec.expand = shufflevector <8 x i8> %0, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+ %1 = bitcast i64 %d.coerce1 to <8 x i8>
+ %d.8.vec.expand = shufflevector <8 x i8> %1, <8 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %d.8.vecblend = shufflevector <16 x i8> %d.8.vec.expand, <16 x i8> %d.0.vec.expand, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %2 = tail call i32 @llvm.mips.bnz.b(<16 x i8> %d.8.vecblend)
+ %tobool = icmp eq i32 %2, 0
+ br i1 %tobool, label %return, label %if.then
+
+ if.then:
+ tail call void asm sideeffect ".space 810680", "~{$1}"()
+ br label %return
+
+ return:
+ %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
+ ret i32 %retval.0
+ }
+
+ declare i32 @llvm.mips.bnz.b(<16 x i8>)
+
+ define i32 @_Z6bnz_16Dv8_s(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
+ entry:
+ %0 = bitcast i64 %d.coerce0 to <4 x i16>
+ %d.0.vec.expand = shufflevector <4 x i16> %0, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
+ %1 = bitcast i64 %d.coerce1 to <4 x i16>
+ %d.8.vec.expand = shufflevector <4 x i16> %1, <4 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3>
+ %d.8.vecblend = shufflevector <8 x i16> %d.8.vec.expand, <8 x i16> %d.0.vec.expand, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
+ %2 = tail call i32 @llvm.mips.bnz.h(<8 x i16> %d.8.vecblend)
+ %tobool = icmp eq i32 %2, 0
+ br i1 %tobool, label %return, label %if.then
+
+ if.then:
+ tail call void asm sideeffect ".space 810680", "~{$1}"()
+ br label %return
+
+ return:
+ %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
+ ret i32 %retval.0
+ }
+
+ declare i32 @llvm.mips.bnz.h(<8 x i16>)
+
+ define i32 @_Z6bnz_32Dv4_i(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
+ entry:
+ %0 = bitcast i64 %d.coerce0 to <2 x i32>
+ %d.0.vec.expand = shufflevector <2 x i32> %0, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+ %1 = bitcast i64 %d.coerce1 to <2 x i32>
+ %d.8.vec.expand = shufflevector <2 x i32> %1, <2 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
+ %d.8.vecblend = shufflevector <4 x i32> %d.8.vec.expand, <4 x i32> %d.0.vec.expand, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+ %2 = tail call i32 @llvm.mips.bnz.w(<4 x i32> %d.8.vecblend)
+ %tobool = icmp eq i32 %2, 0
+ br i1 %tobool, label %return, label %if.then
+
+ if.then:
+ tail call void asm sideeffect ".space 810680", "~{$1}"()
+ br label %return
+
+ return:
+ %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
+ ret i32 %retval.0
+ }
+
+ declare i32 @llvm.mips.bnz.w(<4 x i32>)
+
+ define i32 @_Z6bnz_64Dv2_x(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
+ entry:
+ %d.0.vec.insert = insertelement <2 x i64> undef, i64 %d.coerce0, i32 0
+ %d.8.vec.insert = insertelement <2 x i64> %d.0.vec.insert, i64 %d.coerce1, i32 1
+ %0 = tail call i32 @llvm.mips.bnz.d(<2 x i64> %d.8.vec.insert)
+ %tobool = icmp eq i32 %0, 0
+ br i1 %tobool, label %return, label %if.then
+
+ if.then:
+ tail call void asm sideeffect ".space 810680", "~{$1}"()
+ br label %return
+
+ return:
+ %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
+ ret i32 %retval.0
+ }
+
+ declare i32 @llvm.mips.bnz.d(<2 x i64>)
+
+ define i32 @_Z6bnz_64_vDv2_x(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
+ entry:
+ %d.0.vec.insert = insertelement <2 x i64> undef, i64 %d.coerce0, i32 0
+ %d.8.vec.insert = insertelement <2 x i64> %d.0.vec.insert, i64 %d.coerce1, i32 1
+ %d.16.vec.insert = bitcast <2 x i64> %d.8.vec.insert to <16 x i8>
+ %0 = tail call i32 @llvm.mips.bnz.v(<16 x i8> %d.16.vec.insert)
+ %tobool = icmp eq i32 %0, 0
+ br i1 %tobool, label %return, label %if.then
+
+ if.then:
+ tail call void asm sideeffect ".space 810680", "~{$1}"()
+ br label %return
+
+ return:
+ %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
+ ret i32 %retval.0
+ }
+
+ declare i32 @llvm.mips.bnz.v(<16 x i8>)
+
+...
+---
+name: _Z4bz_8Dv16_a
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$a1_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MSA-LABEL: name: _Z4bz_8Dv16_a
+ ; MSA: bb.0.entry:
+ ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MSA: renamable $w0 = LDI_B 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; MSA: renamable $w0 = SHF_B killed renamable $w0, 27
+ ; MSA: renamable $w0 = SHF_W killed renamable $w0, 177
+ ; MSA: BNZ_B $w0, %bb.2, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.1.entry:
+ ; MSA: successors: %bb.3(0x80000000)
+ ; MSA: J %bb.3, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.2.if.then:
+ ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: }
+ ; MSA: bb.3:
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: }
+ ; PIC-LABEL: name: _Z4bz_8Dv16_a
+ ; PIC: bb.0.entry:
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $w0 = LDI_B 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; PIC: renamable $w0 = SHF_B killed renamable $w0, 27
+ ; PIC: renamable $w0 = SHF_W killed renamable $w0, 177
+ ; PIC: BNZ_B $w0, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1.entry:
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2.entry:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.if.then:
+ ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: }
+ ; PIC: bb.4:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: }
+ bb.0.entry:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64, $a1_64
+
+ renamable $w0 = LDI_B 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ renamable $w0 = SHF_B killed renamable $w0, 27
+ renamable $w0 = SHF_W killed renamable $w0, 177
+ BZ_B killed renamable $w0, %bb.2, implicit-def dead $at
+
+ bb.1.if.then:
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ renamable $v0 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+ bb.2:
+ renamable $v0 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+...
+---
+name: _Z5bz_16Dv8_s
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$a1_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MSA-LABEL: name: _Z5bz_16Dv8_s
+ ; MSA: bb.0.entry:
+ ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MSA: renamable $w0 = LDI_B 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; MSA: renamable $w0 = SHF_H killed renamable $w0, 27
+ ; MSA: BNZ_H $w0, %bb.2, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.1.entry:
+ ; MSA: successors: %bb.3(0x80000000)
+ ; MSA: J %bb.3, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.2.if.then:
+ ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: }
+ ; MSA: bb.3:
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: }
+ ; PIC-LABEL: name: _Z5bz_16Dv8_s
+ ; PIC: bb.0.entry:
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $w0 = LDI_B 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; PIC: renamable $w0 = SHF_H killed renamable $w0, 27
+ ; PIC: BNZ_H $w0, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1.entry:
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2.entry:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.if.then:
+ ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: }
+ ; PIC: bb.4:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: }
+ bb.0.entry:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64, $a1_64
+
+ renamable $w0 = LDI_B 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ renamable $w0 = SHF_H killed renamable $w0, 27
+ BZ_H killed renamable $w0, %bb.2, implicit-def dead $at
+
+ bb.1.if.then:
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ renamable $v0 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+ bb.2:
+ renamable $v0 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+...
+---
+name: _Z5bz_32Dv4_i
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$a1_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MSA-LABEL: name: _Z5bz_32Dv4_i
+ ; MSA: bb.0.entry:
+ ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MSA: renamable $w0 = LDI_B 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; MSA: renamable $w0 = SHF_W killed renamable $w0, 177
+ ; MSA: BNZ_W $w0, %bb.2, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.1.entry:
+ ; MSA: successors: %bb.3(0x80000000)
+ ; MSA: J %bb.3, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.2.if.then:
+ ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: }
+ ; MSA: bb.3:
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: }
+ ; PIC-LABEL: name: _Z5bz_32Dv4_i
+ ; PIC: bb.0.entry:
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $w0 = LDI_B 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; PIC: renamable $w0 = SHF_W killed renamable $w0, 177
+ ; PIC: BNZ_W $w0, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1.entry:
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2.entry:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.if.then:
+ ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: }
+ ; PIC: bb.4:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: }
+ bb.0.entry:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64, $a1_64
+
+ renamable $w0 = LDI_B 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ renamable $w0 = SHF_W killed renamable $w0, 177
+ BZ_W killed renamable $w0, %bb.2, implicit-def dead $at
+
+ bb.1.if.then:
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ renamable $v0 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+ bb.2:
+ renamable $v0 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+...
+---
+name: _Z5bz_64Dv2_x
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$a1_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MSA-LABEL: name: _Z5bz_64Dv2_x
+ ; MSA: bb.0.entry:
+ ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MSA: renamable $w0 = LDI_B 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; MSA: BNZ_D $w0, %bb.2, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.1.entry:
+ ; MSA: successors: %bb.3(0x80000000)
+ ; MSA: J %bb.3, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.2.if.then:
+ ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: }
+ ; MSA: bb.3:
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: }
+ ; PIC-LABEL: name: _Z5bz_64Dv2_x
+ ; PIC: bb.0.entry:
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $w0 = LDI_B 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; PIC: BNZ_D $w0, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1.entry:
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2.entry:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.if.then:
+ ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: }
+ ; PIC: bb.4:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: }
+ bb.0.entry:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64, $a1_64
+
+ renamable $w0 = LDI_B 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ BZ_D killed renamable $w0, %bb.2, implicit-def dead $at
+
+ bb.1.if.then:
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ renamable $v0 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+ bb.2:
+ renamable $v0 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+...
+---
+name: _Z5bz_64_vDv2_x
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$a1_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MSA-LABEL: name: _Z5bz_64_vDv2_x
+ ; MSA: bb.0.entry:
+ ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MSA: renamable $w0 = LDI_B 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; MSA: BNZ_V $w0, %bb.2, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.1.entry:
+ ; MSA: successors: %bb.3(0x80000000)
+ ; MSA: J %bb.3, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.2.if.then:
+ ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: }
+ ; MSA: bb.3:
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: }
+ ; PIC-LABEL: name: _Z5bz_64_vDv2_x
+ ; PIC: bb.0.entry:
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $w0 = LDI_B 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; PIC: BNZ_V $w0, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1.entry:
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2.entry:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.if.then:
+ ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: }
+ ; PIC: bb.4:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: }
+ bb.0.entry:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64, $a1_64
+
+ renamable $w0 = LDI_B 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ BZ_V killed renamable $w0, %bb.2, implicit-def dead $at
+
+ bb.1.if.then:
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ renamable $v0 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+ bb.2:
+ renamable $v0 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+...
+---
+name: _Z5bnz_8Dv16_a
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$a1_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MSA-LABEL: name: _Z5bnz_8Dv16_a
+ ; MSA: bb.0.entry:
+ ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MSA: renamable $w0 = LDI_B 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; MSA: renamable $w0 = SHF_B killed renamable $w0, 27
+ ; MSA: renamable $w0 = SHF_W killed renamable $w0, 177
+ ; MSA: BZ_B $w0, %bb.2, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.1.entry:
+ ; MSA: successors: %bb.3(0x80000000)
+ ; MSA: J %bb.3, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.2.if.then:
+ ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: }
+ ; MSA: bb.3:
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: }
+ ; PIC-LABEL: name: _Z5bnz_8Dv16_a
+ ; PIC: bb.0.entry:
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $w0 = LDI_B 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; PIC: renamable $w0 = SHF_B killed renamable $w0, 27
+ ; PIC: renamable $w0 = SHF_W killed renamable $w0, 177
+ ; PIC: BZ_B $w0, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1.entry:
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2.entry:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.if.then:
+ ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: }
+ ; PIC: bb.4:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: }
+ bb.0.entry:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64, $a1_64
+
+ renamable $w0 = LDI_B 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ renamable $w0 = SHF_B killed renamable $w0, 27
+ renamable $w0 = SHF_W killed renamable $w0, 177
+ BNZ_B killed renamable $w0, %bb.2, implicit-def dead $at
+
+ bb.1.if.then:
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ renamable $v0 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+ bb.2:
+ renamable $v0 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+...
+---
+name: _Z6bnz_16Dv8_s
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$a1_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MSA-LABEL: name: _Z6bnz_16Dv8_s
+ ; MSA: bb.0.entry:
+ ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MSA: renamable $w0 = LDI_B 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; MSA: renamable $w0 = SHF_H killed renamable $w0, 27
+ ; MSA: BZ_H $w0, %bb.2, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.1.entry:
+ ; MSA: successors: %bb.3(0x80000000)
+ ; MSA: J %bb.3, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.2.if.then:
+ ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: }
+ ; MSA: bb.3:
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: }
+ ; PIC-LABEL: name: _Z6bnz_16Dv8_s
+ ; PIC: bb.0.entry:
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $w0 = LDI_B 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; PIC: renamable $w0 = SHF_H killed renamable $w0, 27
+ ; PIC: BZ_H $w0, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1.entry:
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2.entry:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.if.then:
+ ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: }
+ ; PIC: bb.4:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: }
+ bb.0.entry:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64, $a1_64
+
+ renamable $w0 = LDI_B 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ renamable $w0 = SHF_H killed renamable $w0, 27
+ BNZ_H killed renamable $w0, %bb.2, implicit-def dead $at
+
+ bb.1.if.then:
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ renamable $v0 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+ bb.2:
+ renamable $v0 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+...
+---
+name: _Z6bnz_32Dv4_i
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$a1_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MSA-LABEL: name: _Z6bnz_32Dv4_i
+ ; MSA: bb.0.entry:
+ ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MSA: renamable $w0 = LDI_B 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; MSA: renamable $w0 = SHF_W killed renamable $w0, 177
+ ; MSA: BZ_W $w0, %bb.2, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.1.entry:
+ ; MSA: successors: %bb.3(0x80000000)
+ ; MSA: J %bb.3, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.2.if.then:
+ ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: }
+ ; MSA: bb.3:
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: }
+ ; PIC-LABEL: name: _Z6bnz_32Dv4_i
+ ; PIC: bb.0.entry:
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $w0 = LDI_B 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; PIC: renamable $w0 = SHF_W killed renamable $w0, 177
+ ; PIC: BZ_W $w0, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1.entry:
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2.entry:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.if.then:
+ ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: }
+ ; PIC: bb.4:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: }
+ bb.0.entry:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64, $a1_64
+
+ renamable $w0 = LDI_B 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ renamable $w0 = SHF_W killed renamable $w0, 177
+ BNZ_W killed renamable $w0, %bb.2, implicit-def dead $at
+
+ bb.1.if.then:
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ renamable $v0 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+ bb.2:
+ renamable $v0 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+...
+---
+name: _Z6bnz_64Dv2_x
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$a1_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MSA-LABEL: name: _Z6bnz_64Dv2_x
+ ; MSA: bb.0.entry:
+ ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MSA: renamable $w0 = LDI_B 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; MSA: BZ_D $w0, %bb.2, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.1.entry:
+ ; MSA: successors: %bb.3(0x80000000)
+ ; MSA: J %bb.3, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.2.if.then:
+ ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: }
+ ; MSA: bb.3:
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: }
+ ; PIC-LABEL: name: _Z6bnz_64Dv2_x
+ ; PIC: bb.0.entry:
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $w0 = LDI_B 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; PIC: BZ_D $w0, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1.entry:
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2.entry:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.if.then:
+ ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: }
+ ; PIC: bb.4:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: }
+ bb.0.entry:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64, $a1_64
+
+ renamable $w0 = LDI_B 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ BNZ_D killed renamable $w0, %bb.2, implicit-def dead $at
+
+ bb.1.if.then:
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ renamable $v0 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+ bb.2:
+ renamable $v0 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+...
+---
+name: _Z6bnz_64_vDv2_x
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+liveins:
+ - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$a1_64', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ ; MSA-LABEL: name: _Z6bnz_64_vDv2_x
+ ; MSA: bb.0.entry:
+ ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; MSA: renamable $w0 = LDI_B 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; MSA: BZ_V $w0, %bb.2, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.1.entry:
+ ; MSA: successors: %bb.3(0x80000000)
+ ; MSA: J %bb.3, implicit-def $at {
+ ; MSA: NOP
+ ; MSA: }
+ ; MSA: bb.2.if.then:
+ ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: }
+ ; MSA: bb.3:
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: }
+ ; PIC-LABEL: name: _Z6bnz_64_vDv2_x
+ ; PIC: bb.0.entry:
+ ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; PIC: renamable $w0 = LDI_B 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; PIC: BZ_V $w0, %bb.3, implicit-def $at {
+ ; PIC: NOP
+ ; PIC: }
+ ; PIC: bb.1.entry:
+ ; PIC: successors: %bb.2(0x80000000)
+ ; PIC: $sp_64 = DADDiu $sp_64, -16
+ ; PIC: SD $ra_64, $sp_64, 0
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at_64 = DSLL $at_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $ra {
+ ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: }
+ ; PIC: bb.2.entry:
+ ; PIC: successors: %bb.4(0x80000000)
+ ; PIC: $at_64 = DADDu $ra_64, $at_64
+ ; PIC: $ra_64 = LD $sp_64, 0
+ ; PIC: JR64 $at_64 {
+ ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: }
+ ; PIC: bb.3.if.then:
+ ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: }
+ ; PIC: bb.4:
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
+ ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: }
+ bb.0.entry:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $a0_64, $a1_64
+
+ renamable $w0 = LDI_B 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ BNZ_V killed renamable $w0, %bb.2, implicit-def dead $at
+
+ bb.1.if.then:
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ renamable $v0 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+ bb.2:
+ renamable $v0 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $v0
+
+...
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