[llvm] r332442 - [AArch64][SVE] Asm: Support for structured LD2, LD3 and LD4 (scalar+scalar) load instructions.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Wed May 16 02:16:21 PDT 2018
Author: s.desmalen
Date: Wed May 16 02:16:20 2018
New Revision: 332442
URL: http://llvm.org/viewvc/llvm-project?rev=332442&view=rev
Log:
[AArch64][SVE] Asm: Support for structured LD2, LD3 and LD4 (scalar+scalar) load instructions.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D46679
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
llvm/trunk/test/MC/AArch64/SVE/ld2b-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld2b.s
llvm/trunk/test/MC/AArch64/SVE/ld2d-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld2d.s
llvm/trunk/test/MC/AArch64/SVE/ld2h-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld2h.s
llvm/trunk/test/MC/AArch64/SVE/ld2w-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld2w.s
llvm/trunk/test/MC/AArch64/SVE/ld3b-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld3b.s
llvm/trunk/test/MC/AArch64/SVE/ld3d-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld3d.s
llvm/trunk/test/MC/AArch64/SVE/ld3h-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld3h.s
llvm/trunk/test/MC/AArch64/SVE/ld3w-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld3w.s
llvm/trunk/test/MC/AArch64/SVE/ld4b-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld4b.s
llvm/trunk/test/MC/AArch64/SVE/ld4d-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld4d.s
llvm/trunk/test/MC/AArch64/SVE/ld4h-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld4h.s
llvm/trunk/test/MC/AArch64/SVE/ld4w-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld4w.s
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Wed May 16 02:16:20 2018
@@ -134,6 +134,20 @@ let Predicates = [HasSVE] in {
defm LD3D_IMM : sve_mem_eld_si<0b11, 0b10, ZZZ_d, "ld3d", simm4s3>;
defm LD4D_IMM : sve_mem_eld_si<0b11, 0b11, ZZZZ_d, "ld4d", simm4s4>;
+ // LD(2|3|4) structured loads (register + register)
+ def LD2B : sve_mem_eld_ss<0b00, 0b01, ZZ_b, "ld2b", GPR64NoXZRshifted8>;
+ def LD3B : sve_mem_eld_ss<0b00, 0b10, ZZZ_b, "ld3b", GPR64NoXZRshifted8>;
+ def LD4B : sve_mem_eld_ss<0b00, 0b11, ZZZZ_b, "ld4b", GPR64NoXZRshifted8>;
+ def LD2H : sve_mem_eld_ss<0b01, 0b01, ZZ_h, "ld2h", GPR64NoXZRshifted16>;
+ def LD3H : sve_mem_eld_ss<0b01, 0b10, ZZZ_h, "ld3h", GPR64NoXZRshifted16>;
+ def LD4H : sve_mem_eld_ss<0b01, 0b11, ZZZZ_h, "ld4h", GPR64NoXZRshifted16>;
+ def LD2W : sve_mem_eld_ss<0b10, 0b01, ZZ_s, "ld2w", GPR64NoXZRshifted32>;
+ def LD3W : sve_mem_eld_ss<0b10, 0b10, ZZZ_s, "ld3w", GPR64NoXZRshifted32>;
+ def LD4W : sve_mem_eld_ss<0b10, 0b11, ZZZZ_s, "ld4w", GPR64NoXZRshifted32>;
+ def LD2D : sve_mem_eld_ss<0b11, 0b01, ZZ_d, "ld2d", GPR64NoXZRshifted64>;
+ def LD3D : sve_mem_eld_ss<0b11, 0b10, ZZZ_d, "ld3d", GPR64NoXZRshifted64>;
+ def LD4D : sve_mem_eld_ss<0b11, 0b11, ZZZZ_d, "ld4d", GPR64NoXZRshifted64>;
+
// Gathers using unscaled 32-bit offsets, e.g.
// ld1h z0.s, p0/z, [x0, z0.s, uxtw]
defm GLD1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Wed May 16 02:16:20 2018
@@ -1159,6 +1159,28 @@ multiclass sve_mem_eld_si<bits<2> sz, bi
(!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
}
+class sve_mem_eld_ss<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
+ string asm, RegisterOperand gprty>
+: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+ asm, "\t$Zt, $Pg/z, [$Rn, $Rm]",
+ "",
+ []>, Sched<[]> {
+ bits<3> Pg;
+ bits<5> Rm;
+ bits<5> Rn;
+ bits<5> Zt;
+ let Inst{31-25} = 0b1010010;
+ let Inst{24-23} = sz;
+ let Inst{22-21} = nregs;
+ let Inst{20-16} = Rm;
+ let Inst{15-13} = 0b110;
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Zt;
+
+ let mayLoad = 1;
+}
+
//===----------------------------------------------------------------------===//
// SVE Memory - 32-bit Gather and Unsized Contiguous Group
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/MC/AArch64/SVE/ld2b-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld2b-diagnostics.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld2b-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld2b-diagnostics.s Wed May 16 02:16:20 2018
@@ -30,6 +30,30 @@ ld2b {z7.b, z8.b}, p3/z, [x1, #5, MUL VL
// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld2b { z0.b, z1.b }, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: ld2b { z0.b, z1.b }, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld2b { z0.b, z1.b }, p0/z, [x0, x0, lsl #1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: ld2b { z0.b, z1.b }, p0/z, [x0, x0, lsl #1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld2b { z0.b, z1.b }, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: ld2b { z0.b, z1.b }, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld2b { z0.b, z1.b }, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: ld2b { z0.b, z1.b }, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
ld2b {z2.b, z3.b}, p8/z, [x15, #10, MUL VL]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld2b.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld2b.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld2b.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld2b.s Wed May 16 02:16:20 2018
@@ -7,6 +7,18 @@
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+ld2b { z0.b, z1.b }, p0/z, [x0, x0]
+// CHECK-INST: ld2b { z0.b, z1.b }, p0/z, [x0, x0]
+// CHECK-ENCODING: [0x00,0xc0,0x20,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 20 a4 <unknown>
+
+ld2b { z5.b, z6.b }, p3/z, [x17, x16]
+// CHECK-INST: ld2b { z5.b, z6.b }, p3/z, [x17, x16]
+// CHECK-ENCODING: [0x25,0xce,0x30,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 ce 30 a4 <unknown>
+
ld2b { z0.b, z1.b }, p0/z, [x0]
// CHECK-INST: ld2b { z0.b, z1.b }, p0/z, [x0]
// CHECK-ENCODING: [0x00,0xe0,0x20,0xa4]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld2d-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld2d-diagnostics.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld2d-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld2d-diagnostics.s Wed May 16 02:16:20 2018
@@ -30,6 +30,35 @@ ld2d {z7.d, z8.d}, p3/z, [x1, #5, MUL VL
// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld2d { z0.d, z1.d }, p0/z, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: ld2d { z0.d, z1.d }, p0/z, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld2d { z0.d, z1.d }, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: ld2d { z0.d, z1.d }, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld2d { z0.d, z1.d }, p0/z, [x0, x0, lsl #2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: ld2d { z0.d, z1.d }, p0/z, [x0, x0, lsl #2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld2d { z0.d, z1.d }, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: ld2d { z0.d, z1.d }, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld2d { z0.d, z1.d }, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: ld2d { z0.d, z1.d }, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
ld2d {z2.d, z3.d}, p8/z, [x15, #10, MUL VL]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld2d.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld2d.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld2d.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld2d.s Wed May 16 02:16:20 2018
@@ -7,6 +7,18 @@
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+ld2d { z0.d, z1.d }, p0/z, [x0, x0, lsl #3]
+// CHECK-INST: ld2d { z0.d, z1.d }, p0/z, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0xc0,0xa0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 a0 a5 <unknown>
+
+ld2d { z5.d, z6.d }, p3/z, [x17, x16, lsl #3]
+// CHECK-INST: ld2d { z5.d, z6.d }, p3/z, [x17, x16, lsl #3]
+// CHECK-ENCODING: [0x25,0xce,0xb0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 ce b0 a5 <unknown>
+
ld2d { z0.d, z1.d }, p0/z, [x0]
// CHECK-INST: ld2d { z0.d, z1.d }, p0/z, [x0]
// CHECK-ENCODING: [0x00,0xe0,0xa0,0xa5]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld2h-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld2h-diagnostics.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld2h-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld2h-diagnostics.s Wed May 16 02:16:20 2018
@@ -30,6 +30,35 @@ ld2h {z7.h, z8.h}, p3/z, [x1, #5, MUL VL
// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld2h { z0.h, z1.h }, p0/z, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld2h { z0.h, z1.h }, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld2h { z0.h, z1.h }, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld2h { z0.h, z1.h }, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
ld2h {z2.h, z3.h}, p8/z, [x15, #10, MUL VL]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld2h.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld2h.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld2h.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld2h.s Wed May 16 02:16:20 2018
@@ -7,6 +7,18 @@
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #1]
+// CHECK-INST: ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0xc0,0xa0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 a0 a4 <unknown>
+
+ld2h { z5.h, z6.h }, p3/z, [x17, x16, lsl #1]
+// CHECK-INST: ld2h { z5.h, z6.h }, p3/z, [x17, x16, lsl #1]
+// CHECK-ENCODING: [0x25,0xce,0xb0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 ce b0 a4 <unknown>
+
ld2h { z0.h, z1.h }, p0/z, [x0]
// CHECK-INST: ld2h { z0.h, z1.h }, p0/z, [x0]
// CHECK-ENCODING: [0x00,0xe0,0xa0,0xa4]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld2w-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld2w-diagnostics.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld2w-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld2w-diagnostics.s Wed May 16 02:16:20 2018
@@ -30,6 +30,35 @@ ld2w {z7.s, z8.s}, p3/z, [x1, #5, MUL VL
// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld2w { z0.s, z1.s }, p0/z, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: ld2w { z0.s, z1.s }, p0/z, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld2w { z0.s, z1.s }, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: ld2w { z0.s, z1.s }, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld2w { z0.s, z1.s }, p0/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: ld2w { z0.s, z1.s }, p0/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld2w { z0.s, z1.s }, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: ld2w { z0.s, z1.s }, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld2w { z0.s, z1.s }, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: ld2w { z0.s, z1.s }, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
ld2w {z2.s, z3.s}, p8/z, [x15, #10, MUL VL]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld2w.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld2w.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld2w.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld2w.s Wed May 16 02:16:20 2018
@@ -7,6 +7,18 @@
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+ld2w { z0.s, z1.s }, p0/z, [x0, x0, lsl #2]
+// CHECK-INST: ld2w { z0.s, z1.s }, p0/z, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0xc0,0x20,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 20 a5 <unknown>
+
+ld2w { z5.s, z6.s }, p3/z, [x17, x16, lsl #2]
+// CHECK-INST: ld2w { z5.s, z6.s }, p3/z, [x17, x16, lsl #2]
+// CHECK-ENCODING: [0x25,0xce,0x30,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 ce 30 a5 <unknown>
+
ld2w { z0.s, z1.s }, p0/z, [x0]
// CHECK-INST: ld2w { z0.s, z1.s }, p0/z, [x0]
// CHECK-ENCODING: [0x00,0xe0,0x20,0xa5]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld3b-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld3b-diagnostics.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld3b-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld3b-diagnostics.s Wed May 16 02:16:20 2018
@@ -30,6 +30,30 @@ ld3b {z7.b, z8.b, z9.b}, p3/z, [x1, #5,
// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, x0, lsl #1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, x0, lsl #1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
ld3b {z2.b, z3.b, z4.b}, p8/z, [x15, #10, MUL VL]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld3b.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld3b.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld3b.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld3b.s Wed May 16 02:16:20 2018
@@ -7,6 +7,18 @@
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, x0]
+// CHECK-INST: ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, x0]
+// CHECK-ENCODING: [0x00,0xc0,0x40,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 40 a4 <unknown>
+
+ld3b { z5.b, z6.b, z7.b }, p3/z, [x17, x16]
+// CHECK-INST: ld3b { z5.b, z6.b, z7.b }, p3/z, [x17, x16]
+// CHECK-ENCODING: [0x25,0xce,0x50,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 ce 50 a4 <unknown>
+
ld3b { z0.b, z1.b, z2.b }, p0/z, [x0]
// CHECK-INST: ld3b { z0.b, z1.b, z2.b }, p0/z, [x0]
// CHECK-ENCODING: [0x00,0xe0,0x40,0xa4]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld3d-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld3d-diagnostics.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld3d-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld3d-diagnostics.s Wed May 16 02:16:20 2018
@@ -30,6 +30,35 @@ ld3d {z7.d, z8.d, z9.d}, p3/z, [x1, #5,
// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, x0, lsl #2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, x0, lsl #2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
ld3d {z2.d, z3.d, z4.d}, p8/z, [x15, #10, MUL VL]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld3d.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld3d.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld3d.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld3d.s Wed May 16 02:16:20 2018
@@ -7,6 +7,18 @@
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, x0, lsl #3]
+// CHECK-INST: ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0xc0,0xc0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 c0 a5 <unknown>
+
+ld3d { z5.d, z6.d, z7.d }, p3/z, [x17, x16, lsl #3]
+// CHECK-INST: ld3d { z5.d, z6.d, z7.d }, p3/z, [x17, x16, lsl #3]
+// CHECK-ENCODING: [0x25,0xce,0xd0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 ce d0 a5 <unknown>
+
ld3d { z0.d, z1.d, z2.d }, p0/z, [x0]
// CHECK-INST: ld3d { z0.d, z1.d, z2.d }, p0/z, [x0]
// CHECK-ENCODING: [0x00,0xe0,0xc0,0xa5]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld3h-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld3h-diagnostics.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld3h-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld3h-diagnostics.s Wed May 16 02:16:20 2018
@@ -30,6 +30,35 @@ ld3h {z7.h, z8.h, z9.h}, p3/z, [x1, #5,
// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, x0, lsl #2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, x0, lsl #2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
ld3h {z2.h, z3.h, z4.h}, p8/z, [x15, #10, MUL VL]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld3h.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld3h.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld3h.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld3h.s Wed May 16 02:16:20 2018
@@ -7,6 +7,18 @@
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, x0, lsl #1]
+// CHECK-INST: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0xc0,0xc0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 c0 a4 <unknown>
+
+ld3h { z5.h, z6.h, z7.h }, p3/z, [x17, x16, lsl #1]
+// CHECK-INST: ld3h { z5.h, z6.h, z7.h }, p3/z, [x17, x16, lsl #1]
+// CHECK-ENCODING: [0x25,0xce,0xd0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 ce d0 a4 <unknown>
+
ld3h { z0.h, z1.h, z2.h }, p0/z, [x0]
// CHECK-INST: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0]
// CHECK-ENCODING: [0x00,0xe0,0xc0,0xa4]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld3w-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld3w-diagnostics.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld3w-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld3w-diagnostics.s Wed May 16 02:16:20 2018
@@ -30,6 +30,35 @@ ld3w {z7.s, z8.s, z9.s}, p3/z, [x1, #5,
// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
ld3w {z2.s, z3.s, z4.s}, p8/z, [x15, #10, MUL VL]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld3w.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld3w.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld3w.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld3w.s Wed May 16 02:16:20 2018
@@ -7,6 +7,18 @@
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, x0, lsl #2]
+// CHECK-INST: ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0xc0,0x40,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 40 a5 <unknown>
+
+ld3w { z5.s, z6.s, z7.s }, p3/z, [x17, x16, lsl #2]
+// CHECK-INST: ld3w { z5.s, z6.s, z7.s }, p3/z, [x17, x16, lsl #2]
+// CHECK-ENCODING: [0x25,0xce,0x50,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 ce 50 a5 <unknown>
+
ld3w { z0.s, z1.s, z2.s }, p0/z, [x0]
// CHECK-INST: ld3w { z0.s, z1.s, z2.s }, p0/z, [x0]
// CHECK-ENCODING: [0x00,0xe0,0x40,0xa5]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld4b-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld4b-diagnostics.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld4b-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld4b-diagnostics.s Wed May 16 02:16:20 2018
@@ -30,6 +30,30 @@ ld4b {z7.b, z8.b, z9.b, z10.b}, p3/z, [x
// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x0, lsl #1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x0, lsl #1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
+// CHECK-NEXT: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
ld4b {z2.b, z3.b, z4.b, z5.b}, p8/z, [x15, #10, MUL VL]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld4b.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld4b.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld4b.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld4b.s Wed May 16 02:16:20 2018
@@ -7,6 +7,18 @@
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x0]
+// CHECK-INST: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x0]
+// CHECK-ENCODING: [0x00,0xc0,0x60,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 60 a4 <unknown>
+
+ld4b { z5.b, z6.b, z7.b, z8.b }, p3/z, [x17, x16]
+// CHECK-INST: ld4b { z5.b, z6.b, z7.b, z8.b }, p3/z, [x17, x16]
+// CHECK-ENCODING: [0x25,0xce,0x70,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 ce 70 a4 <unknown>
+
ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0]
// CHECK-INST: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0]
// CHECK-ENCODING: [0x00,0xe0,0x60,0xa4]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld4d-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld4d-diagnostics.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld4d-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld4d-diagnostics.s Wed May 16 02:16:20 2018
@@ -30,6 +30,35 @@ ld4d {z7.d, z8.d, z9.d, z10.d}, p3/z, [x
// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
+// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
ld4d {z2.d, z3.d, z4.d, z5.d}, p8/z, [x15, #10, MUL VL]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld4d.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld4d.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld4d.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld4d.s Wed May 16 02:16:20 2018
@@ -7,6 +7,18 @@
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #3]
+// CHECK-INST: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0xc0,0xe0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 e0 a5 <unknown>
+
+ld4d { z5.d, z6.d, z7.d, z8.d }, p3/z, [x17, x16, lsl #3]
+// CHECK-INST: ld4d { z5.d, z6.d, z7.d, z8.d }, p3/z, [x17, x16, lsl #3]
+// CHECK-ENCODING: [0x25,0xce,0xf0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 ce f0 a5 <unknown>
+
ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0]
// CHECK-INST: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0]
// CHECK-ENCODING: [0x00,0xe0,0xe0,0xa5]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld4h-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld4h-diagnostics.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld4h-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld4h-diagnostics.s Wed May 16 02:16:20 2018
@@ -30,6 +30,35 @@ ld4h {z7.h, z8.h, z9.h, z10.h}, p3/z, [x
// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x0, lsl #2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x0, lsl #2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
+// CHECK-NEXT: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
ld4h {z2.h, z3.h, z4.h, z5.h}, p8/z, [x15, #10, MUL VL]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld4h.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld4h.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld4h.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld4h.s Wed May 16 02:16:20 2018
@@ -7,6 +7,18 @@
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x0, lsl #1]
+// CHECK-INST: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0xc0,0xe0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 e0 a4 <unknown>
+
+ld4h { z5.h, z6.h, z7.h, z8.h }, p3/z, [x17, x16, lsl #1]
+// CHECK-INST: ld4h { z5.h, z6.h, z7.h, z8.h }, p3/z, [x17, x16, lsl #1]
+// CHECK-ENCODING: [0x25,0xce,0xf0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 ce f0 a4 <unknown>
+
ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0]
// CHECK-INST: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0]
// CHECK-ENCODING: [0x00,0xe0,0xe0,0xa4]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld4w-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld4w-diagnostics.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld4w-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld4w-diagnostics.s Wed May 16 02:16:20 2018
@@ -30,6 +30,35 @@ ld4w {z7.s, z8.s, z9.s, z10.s}, p3/z, [x
// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
+// CHECK-NEXT: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
ld4w {z2.s, z3.s, z4.s, z5.s}, p8/z, [x15, #10, MUL VL]
Modified: llvm/trunk/test/MC/AArch64/SVE/ld4w.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld4w.s?rev=332442&r1=332441&r2=332442&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld4w.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld4w.s Wed May 16 02:16:20 2018
@@ -7,6 +7,18 @@
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x0, lsl #2]
+// CHECK-INST: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0xc0,0x60,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 60 a5 <unknown>
+
+ld4w { z5.s, z6.s, z7.s, z8.s }, p3/z, [x17, x16, lsl #2]
+// CHECK-INST: ld4w { z5.s, z6.s, z7.s, z8.s }, p3/z, [x17, x16, lsl #2]
+// CHECK-ENCODING: [0x25,0xce,0x70,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 ce 70 a5 <unknown>
+
ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0]
// CHECK-INST: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0]
// CHECK-ENCODING: [0x00,0xe0,0x60,0xa5]
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