[PATCH] D46762: [AArch64] Improve single vector lane unscaled stores

[Eli Friedman via Phabricator via llvm-commits]

efriedma accepted this revision.
efriedma added a comment.
This revision is now accepted and ready to land.

LGTM with a minor comment on the test changes.



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Comment at: llvm/test/CodeGen/AArch64/arm64-st1.ll:72
 ; CHECK-LABEL: st1lane0u_8h
-; CHECK: st1.h
+; CHECK: stur h{{[0-9]+}}, [x{{[0-9]+}}, #-{{[0-9]+}}]
   %ptr = getelementptr i16, i16* %D, i64 -1
----------------
Using patterns rather than the actual instruction doesn't seem helpful here: you know exactly which registers the two inputs will be in, and the exact offset, so the output should be stable.  (Patterns are more useful when the registers aren't predictable, like temporary values.)


Repository:
  rL LLVM

https://reviews.llvm.org/D46762