[llvm] r332365 - [Hexagon] Remove unused flag from subtarget and (non)corresponding test

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Tue May 15 09:13:52 2018
New Revision: 332365

URL: http://llvm.org/viewvc/llvm-project?rev=332365&view=rev
Log:
[Hexagon] Remove unused flag from subtarget and (non)corresponding test

Removed:
    llvm/trunk/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/Hexagon.td
    llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h

Modified: llvm/trunk/lib/Target/Hexagon/Hexagon.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.td?rev=332365&r1=332364&r2=332365&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/Hexagon.td (original)
+++ llvm/trunk/lib/Target/Hexagon/Hexagon.td Tue May 15 09:13:52 2018
@@ -66,7 +66,6 @@ def FeatureReservedR19: SubtargetFeature
 //===----------------------------------------------------------------------===//
 
 def UseMEMOPS          : Predicate<"HST->useMemops()">;
-def IEEERndNearV5T     : Predicate<"HST->modeIEEERndNear()">;
 def UseHVX64B          : Predicate<"HST->useHVX64BOps()">,
                          AssemblerPredicate<"ExtensionHVX64B">;
 def UseHVX128B         : Predicate<"HST->useHVX128BOps()">,

Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp?rev=332365&r1=332364&r2=332365&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp Tue May 15 09:13:52 2018
@@ -40,10 +40,6 @@ using namespace llvm;
 #include "HexagonGenSubtargetInfo.inc"
 
 
-static cl::opt<bool> EnableIEEERndNear("enable-hexagon-ieee-rnd-near",
-  cl::Hidden, cl::ZeroOrMore, cl::init(false),
-  cl::desc("Generate non-chopped conversion from fp to int."));
-
 static cl::opt<bool> EnableBSBSched("enable-bsb-sched",
   cl::Hidden, cl::ZeroOrMore, cl::init(true));
 
@@ -114,7 +110,6 @@ HexagonSubtarget::initializeSubtargetDep
   UseHVX64BOps = false;
   UseLongCalls = false;
 
-  ModeIEEERndNear = EnableIEEERndNear;
   UseBSBScheduling = hasV60TOps() && EnableBSBSched;
 
   ParseSubtargetFeatures(CPUString, FS);

Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h?rev=332365&r1=332364&r2=332365&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h Tue May 15 09:13:52 2018
@@ -48,7 +48,6 @@ class HexagonSubtarget : public HexagonG
 
   bool UseHVX64BOps = false;
   bool UseHVX128BOps = false;
-  bool ModeIEEERndNear = false;
 
   bool UseLongCalls = false;
   bool UseMemops = false;
@@ -162,7 +161,6 @@ public:
   bool useNewValueStores() const { return UseNewValueStores; }
   bool useSmallData() const { return UseSmallData; }
 
-  bool modeIEEERndNear() const { return ModeIEEERndNear; }
   bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::V4; }
   bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
   bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }

Removed: llvm/trunk/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll?rev=332364&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll (removed)
@@ -1,26 +0,0 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-hexagon-ieee-rnd-near < %s | FileCheck %s
-; Check that we generate conversion from double precision floating point
-; to 32-bit int value in IEEE rounding to the nearest mode in V5.
-
-; CHECK: r{{[0-9]+}} = convert_df2w(r{{[0-9]+}}:{{[0-9]+}})
-
-define i32 @main() nounwind {
-entry:
-  %retval = alloca i32, align 4
-  %i = alloca i32, align 4
-  %a = alloca double, align 8
-  %b = alloca double, align 8
-  %c = alloca double, align 8
-  store i32 0, i32* %retval
-  store volatile double 1.540000e+01, double* %a, align 8
-  store volatile double 9.100000e+00, double* %b, align 8
-  %0 = load volatile double, double* %a, align 8
-  %1 = load volatile double, double* %b, align 8
-  %add = fadd double %0, %1
-  store double %add, double* %c, align 8
-  %2 = load double, double* %c, align 8
-  %conv = fptosi double %2 to i32
-  store i32 %conv, i32* %i, align 4
-  %3 = load i32, i32* %i, align 4
-  ret i32 %3
-}