[PATCH] D46674: [RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation

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This revision was automatically updated to reflect the committed changes.
Closed by commit rL332318: [RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker… (authored by shiva, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D46674?vs=146730&id=146731#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D46674

Files:
  llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
  llvm/trunk/lib/Target/RISCV/RISCV.td
  llvm/trunk/lib/Target/RISCV/RISCVSubtarget.h


Index: llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
===================================================================
--- llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -43,6 +43,14 @@
   std::unique_ptr<MCObjectWriter>
   createObjectWriter(raw_pwrite_stream &OS) const override;
 
+  // If linker relaxation is enabled, always emit relocations even if the fixup
+  // can be resolved. This is necessary for correctness as offsets may change
+  // during relaxation.
+  bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
+                             const MCValue &Target) override {
+    return STI.getFeatureBits()[RISCV::FeatureRelax];
+  }
+
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override;
Index: llvm/trunk/lib/Target/RISCV/RISCVSubtarget.h
===================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/trunk/lib/Target/RISCV/RISCVSubtarget.h
@@ -36,6 +36,7 @@
   bool HasStdExtD = false;
   bool HasStdExtC = false;
   bool HasRV64 = false;
+  bool EnableLinkerRelax = false;
   unsigned XLen = 32;
   MVT XLenVT = MVT::i32;
   RISCVFrameLowering FrameLowering;
@@ -77,6 +78,7 @@
   bool hasStdExtD() const { return HasStdExtD; }
   bool hasStdExtC() const { return HasStdExtC; }
   bool is64Bit() const { return HasRV64; }
+  bool enableLinkerRelax() const { return EnableLinkerRelax; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
 };
Index: llvm/trunk/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/trunk/lib/Target/RISCV/RISCV.td
+++ llvm/trunk/lib/Target/RISCV/RISCV.td
@@ -55,6 +55,10 @@
 def RV64           : HwMode<"+64bit">;
 def RV32           : HwMode<"-64bit">;
 
+def FeatureRelax
+    : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
+                       "Enable Linker relaxation.">;
+
 //===----------------------------------------------------------------------===//
 // Registers, calling conventions, instruction descriptions.
 //===----------------------------------------------------------------------===//


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